Semiconductor device and manufacturing method for the same
    4.
    发明申请
    Semiconductor device and manufacturing method for the same 有权
    半导体器件及其制造方法相同

    公开(公告)号:US20070194445A1

    公开(公告)日:2007-08-23

    申请号:US11441067

    申请日:2006-05-26

    申请人: Yoshitaka Aiba

    发明人: Yoshitaka Aiba

    IPC分类号: H01L23/48 H01L23/52 H01L29/40

    摘要: To provide a semiconductor device with high performance and reliability, in which peeling off an interconnection layer caused due to peeling off of a resin film at a land part is suppressed and thus electrical break down is prevented, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor substrate (e.g., a silicon wafer 10); an insulating film 12 formed on the semiconductor substrate 10; a conductive layer 20 formed on the insulating film 12, the conductive layer 20 formed of an interconnection part 22 and a land part 24 which connects the interconnection part 22 to an external terminal 40; and a resin film 30 covering the conductive layer 20, wherein the resin film 30 is in contact with the insulating film 12 at least at a part of the land part 24 by passing through the conductive layer 20.

    摘要翻译: 为了提供一种具有高性能和可靠性的半导体器件,其中抑制了由于在焊盘部分处的树脂膜的剥离引起的互连层的剥离,从而防止了电气故障,并且制造半导体器件的有效方法 。 半导体器件包括半导体衬底(例如,硅晶片10); 形成在半导体衬底10上的绝缘膜12; 形成在绝缘膜12上的导电层20,由互连部22形成的导电层20和将互连部22连接到外部端子40的焊盘部24; 以及覆盖导电层20的树脂膜30,其中树脂膜30通过穿过导电层20至少在陆部24的一部分处与绝缘膜12接触。

    Method of designing circuit board
    10.
    发明授权
    Method of designing circuit board 失效
    电路板设计方法

    公开(公告)号:US07251801B2

    公开(公告)日:2007-07-31

    申请号:US11019156

    申请日:2004-12-23

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068 H05K3/0005

    摘要: A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.

    摘要翻译: 一种能够高效率地绘制高密度导线的电路板的设计方法。 大鼠巢通过连接电子装置的端子的连接垫和通过线路的外部连接端子形成。 然后选择大鼠巢线密度最高的区域,并且在具有最大密度的大鼠巢的区域中设置与导线的路线和尺寸相关的设计规则。 然后将导体线放置在具有最高密度的大鼠巢的区域,并且确定导线是否可以放置在具有最大密度的大鼠巢的密度的区域。 如果导体线不能铺设,则设计规则和布线的设置,如果可以铺设导体线,则通过设定的规则布置其余区域的导体线。