公开(公告)号：US07915538B2

公开(公告)日：2011-03-29

申请号：US12021548

申请日：2008-01-29

申请人： Masamitsu Ikumo ,  Tadahiro Okamoto ,  Eiji Watanabe

发明人： Masamitsu Ikumo ,  Tadahiro Okamoto ,  Eiji Watanabe

IPC分类号： H05K1/03

CPC分类号： H01L23/5385 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/13 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/0052 ,  H05K3/007 ,  H05K3/20 ,  H05K3/28 ,  H05K3/4682 ,  H05K2201/0187 ,  H05K2201/09036 ,  H05K2201/09518 ,  H05K2203/016 ,  Y10T29/49126 ,  Y10T428/24802 ,  Y10T428/24917 ,  H01L2224/0401

摘要： A multilayer wiring board having a plurality of wiring boards in which wiring layers and resin layers in each wiring board are alternately arranged in a laminated formation. In the multilayer wiring board, all the resin layers and the wiring layers, except a resin layer in the plurality of wiring boards, are separated in a same position between the plurality of wiring boards and the resin layer is continuous in the same position.

摘要翻译： 具有多个配线基板的多层布线基板，其中布线层和每个布线板中的树脂层交替地布置在层叠结构中。 在多层布线基板中，除了多个布线基板中的树脂层以外的所有树脂层和布线层在多个布线基板之间的相同位置分离，并且树脂层在相同位置连续。

公开(公告)号：US20080012128A1

公开(公告)日：2008-01-17

申请号：US11703153

申请日：2007-02-07

申请人： Yutaka Makino ,  Tadahiro Okamoto ,  Takaki Kurita

发明人： Yutaka Makino ,  Tadahiro Okamoto ,  Takaki Kurita

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L24/12 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05138 ,  H01L2224/05624 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00

摘要： When a nickel (Ni) layer is formed on an electrode pad made of aluminum-silicon (Al—Si) by an electroless plating method, prior to the precipitation of zinc (Zn) which becomes a catalyst, copper (Cu) is formed in the form of discontinuous spots or islands on the surface of the electrode pad, thereby providing a copper (Cu) thin layer.

摘要翻译： 当通过化学镀法在由铝 - 硅（Al-Si）制成的电极焊盘上形成镍（Ni）层时，在沉淀出成为催化剂的锌（Zn）之前，形成铜（Cu） 在电极焊盘的表面上形成不连续的点或岛，由此提供铜（Cu）薄层。

公开(公告)号：US20060219429A1

公开(公告)日：2006-10-05

申请号：US11180780

申请日：2005-07-14

申请人： Masamitsu Ikumo ,  Tadahiro Okamoto ,  Eiji Watanabe

发明人： Masamitsu Ikumo ,  Tadahiro Okamoto ,  Eiji Watanabe

IPC分类号： H05K1/03 ,  H05K3/36

CPC分类号： H01L23/5385 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/13 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/0052 ,  H05K3/007 ,  H05K3/20 ,  H05K3/28 ,  H05K3/4682 ,  H05K2201/0187 ,  H05K2201/09036 ,  H05K2201/09518 ,  H05K2203/016 ,  Y10T29/49126 ,  Y10T428/24802 ,  Y10T428/24917 ,  H01L2224/0401

摘要： A multilayer wiring board comprises a plurality of wiring boards in which wiring layers and resin layers in each wiring board are alternately arranged in a laminated formation. In the multilayer wiring board, all the resin layers and the wiring layers, except a resin layer in the plurality of wiring boards, are separated in a same position between the plurality of wiring boards and the resin layer is continuous in the same position.

摘要翻译： 多层布线板包括多个布线板，其中布线层和每个布线板中的树脂层以叠层形式交替布置。 在多层布线基板中，除了多个布线基板中的树脂层以外的所有树脂层和布线层在多个布线基板之间的相同位置分离，并且树脂层在相同位置连续。

公开(公告)号：US20060214296A1

公开(公告)日：2006-09-28

申请号：US11156591

申请日：2005-06-21

申请人： Tadahiro Okamoto ,  Masamitsu Ikumo ,  Eiji Watanabe

发明人： Tadahiro Okamoto ,  Masamitsu Ikumo ,  Eiji Watanabe

IPC分类号： H01L23/52

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/11003 ,  H01L2224/1111 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00014

摘要： In a semiconductor-device manufacturing method, a metal bump is formed through a plurality of barrier metal layers on an opening which is selectively formed in an insulation layer covering a semiconductor substrate. The metal bump is formed on the plurality of barrier metal layers. A first etching process that selectively removes a lower metal layer among the plurality of barrier metal layers is performed by using an upper metal layer among the plurality of barrier metal layers as a mask. A reflow process that covers an end face of the lower metal layer with a metal that forms the metal bump is performed. After the lower metal layer end face is covered with the metal, a second etching process that removes a barrier metal residue on a surface of the insulation layer in a circumference of the metal bump is performed.

摘要翻译： 在半导体器件制造方法中，通过选择性地形成在覆盖半导体衬底的绝缘层中的开口上的多个阻挡金属层形成金属凸块。 金属凸块形成在多个阻挡金属层上。 通过使用多个阻挡金属层中的上部金属层作为掩模，进行选择性地去除多个阻挡金属层中的下部金属层的第一蚀刻工艺。 执行用形成金属凸块的金属覆盖下金属层的端面的回流工艺。 在下金属层端面被金属覆盖之后，执行在金属凸块的周围去除绝缘层表面上的阻挡金属残渣的第二蚀刻工艺。

公开(公告)号：US07754534B2

公开(公告)日：2010-07-13

申请号：US12081723

申请日：2008-04-21

申请人： Nobukatsu Saito ,  Masaharu Minamizawa ,  Yoshiyuki Yoneda ,  Nobutaka Shimizu ,  Kazuyuki Imamura ,  Atsushi Kikuchi ,  Tadahiro Okamoto ,  Eiji Watanabe

发明人： Nobukatsu Saito ,  Masaharu Minamizawa ,  Yoshiyuki Yoneda ,  Nobutaka Shimizu ,  Kazuyuki Imamura ,  Atsushi Kikuchi ,  Tadahiro Okamoto ,  Eiji Watanabe

IPC分类号： H01L21/00

CPC分类号： H01L21/6836 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/75315 ,  H01L2224/75755 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.

摘要翻译： 提供一种使用布线基板制造半导体器件的方法，其可以有助于布线基板的处理。 该方法包括以下步骤：在硅基板上形成可剥离树脂层，在可剥离树脂层上形成布线基板，在布线基板上安装半导体芯片，通过密封树脂密封多个半导体芯片形成半导体器件， 半导体器件通过从密封树脂侧切割半导体器件但离开硅衬底，从硅衬底和可剥离树脂层之间的硅衬底剥离每个单独的半导体器件，并且通过形成开口 通过可剥离树脂层或通过除去可剥离树脂层。

公开(公告)号：US07723847B2

公开(公告)日：2010-05-25

申请号：US11703153

申请日：2007-02-07

申请人： Yutaka Makino ,  Tadahiro Okamoto ,  Takaki Kurita

发明人： Yutaka Makino ,  Tadahiro Okamoto ,  Takaki Kurita

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L24/12 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05138 ,  H01L2224/05624 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00

摘要： When a nickel (Ni) layer is formed on an electrode pad made of aluminum-silicon (Al—Si) by an electroless plating method, prior to the precipitation of zinc (Zn) which becomes a catalyst, copper (Cu) is formed in the form of discontinuous spots or islands on the surface of the electrode pad, thereby providing a copper (Cu) thin layer.

摘要翻译： 当通过化学镀法在由铝 - 硅（Al-Si）制成的电极焊盘上形成镍（Ni）层时，在沉淀出成为催化剂的锌（Zn）之前，形成铜（Cu） 在电极焊盘的表面上形成不连续的点或岛，由此提供铜（Cu）薄层。

公开(公告)号：US20060258045A1

公开(公告)日：2006-11-16

申请号：US11412127

申请日：2006-04-27

申请人： Masahiko Ishiguri ,  Hirohisa Matsuki ,  Hiroyuki Yoda ,  Tadahiro Okamoto ,  Masamitsu Ikumo ,  Shuichi Chiba

发明人： Masahiko Ishiguri ,  Hirohisa Matsuki ,  Hiroyuki Yoda ,  Tadahiro Okamoto ,  Masamitsu Ikumo ,  Shuichi Chiba

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2224/13099

摘要： A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to satisfy the relations (X½)≦X2≦(3*X¼) and (X½)≦X3≦(3*X¼).

摘要翻译： 半导体器件包括半导体衬底和以间距X1布置的突出电极阵列。 每个突出电极具有高度X3，并且形成在直径为X2的阻挡金属基底上，耦合到布置在半导体衬底上的电极，以满足关系式（X 1/2）<= X2 <=（3 *X¼）和（ X½）<= X3 <=（3 *X¼）。

公开(公告)号：US20050140004A1

公开(公告)日：2005-06-30

申请号：US10995081

申请日：2004-11-23

申请人： Masahiko Ishiguri ,  Hirohisa Matsuki ,  Hiroyuki Yoda ,  Tadahiro Okamoto ,  Masamitsu Ikumo ,  Shuichi Chiba

发明人： Masahiko Ishiguri ,  Hirohisa Matsuki ,  Hiroyuki Yoda ,  Tadahiro Okamoto ,  Masamitsu Ikumo ,  Shuichi Chiba

IPC分类号： H01L21/60 ,  H01L21/28 ,  H01L21/768 ,  H01L23/02 ,  H01L23/48 ,  H01L23/485 ,  H01L23/52

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2224/13099

摘要： A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to satisfy the relations (X1/2)≦X2≦(3*X1/4) and (X1/2)≦X3≦(3*X1/4).

摘要翻译： 半导体器件包括半导体衬底和以间距X 1布置的突出电极阵列。 每个突出电极具有高度X 3，并且形成在与布置在半导体衬底上的电极耦合的直径为X 2的阻挡金属基底上，以满足关系（X 1/2）<= X 2 <=（ 3 * X 1/4）和（X 1/2）<= X 3 <=（3 * X 1/4）。

公开(公告)号：US20080261336A1

公开(公告)日：2008-10-23

申请号：US12081723

申请日：2008-04-21

申请人： Nobukatsu Saito ,  Masaharu Minamizawa ,  Yoshiyuki Yoneda ,  Nobutaka Shimizu ,  Kazuyuki Imamura ,  Atsushi Kikuchi ,  Tadahiro Okamoto ,  Eiji Watanabe

发明人： Nobukatsu Saito ,  Masaharu Minamizawa ,  Yoshiyuki Yoneda ,  Nobutaka Shimizu ,  Kazuyuki Imamura ,  Atsushi Kikuchi ,  Tadahiro Okamoto ,  Eiji Watanabe

IPC分类号： H01L21/66 ,  H01L21/56

CPC分类号： H01L21/6836 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/75315 ,  H01L2224/75755 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.

摘要翻译： 提供一种使用布线基板制造半导体器件的方法，其可以有助于布线基板的处理。 该方法包括以下步骤：在硅基板上形成可剥离树脂层，在可剥离树脂层上形成布线基板，在布线基板上安装半导体芯片，通过密封树脂密封多个半导体芯片形成半导体器件， 半导体器件通过从密封树脂侧切割半导体器件但离开硅衬底，从硅衬底和可剥离树脂层之间的硅衬底剥离每个单独的半导体器件，并且通过形成开口 通过可剥离树脂层或通过除去可剥离树脂层。

公开(公告)号：US20080124529A1

公开(公告)日：2008-05-29

申请号：US12021548

申请日：2008-01-29

申请人： Masamitsu IKUMO ,  Tadahiro OKAMOTO ,  Eiji WATANABE

发明人： Masamitsu IKUMO ,  Tadahiro OKAMOTO ,  Eiji WATANABE

IPC分类号： B32B3/00

CPC分类号： H01L23/5385 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/13 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/0052 ,  H05K3/007 ,  H05K3/20 ,  H05K3/28 ,  H05K3/4682 ,  H05K2201/0187 ,  H05K2201/09036 ,  H05K2201/09518 ,  H05K2203/016 ,  Y10T29/49126 ,  Y10T428/24802 ,  Y10T428/24917 ,  H01L2224/0401

摘要： A multilayer wiring board having a plurality of wiring boards in which wiring layers and resin layers in each wiring board are alternately arranged in a laminated formation. In the multilayer wiring board, all the resin layers and the wiring layers, except a resin layer in the plurality of wiring boards, are separated in a same position between the plurality of wiring boards and the resin layer is continuous in the same position.

摘要翻译： 具有多个配线基板的多层布线基板，其中布线层和每个布线板中的树脂层交替地布置在层叠结构中。 在多层布线基板中，除了多个布线基板中的树脂层以外的所有树脂层和布线层在多个布线基板之间的相同位置分离，并且树脂层在相同位置连续。