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公开(公告)号：US10032749B2
公开(公告)日：2018-07-24
申请号：US14942708
申请日：2015-11-16
IPC分类号： H01L21/00 , H01L23/48 , H01L25/065 , H01L23/00 , H01L23/538 , H01L25/00 , H01L23/31 , H01L21/56
摘要： An integrated circuit device is disclosed that includes a semiconductor substrate and a die attached to the semiconductor substrate. A conductive pillar is connected to at least one of the semiconductor substrate or the die. An overmold is molded onto the semiconductor substrate over the die, and the conductive pillar extends through the overmold.
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公开(公告)号：US09472451B2
公开(公告)日：2016-10-18
申请号：US14512506
申请日：2014-10-13
IPC分类号： H01L23/48 , H01L23/52 , H01L21/768 , H01L23/29 , H01L21/56 , H01L23/50 , H01L23/31 , H01L23/00 , H01L25/065 , H01L23/28
CPC分类号： H01L21/76877 , H01L21/56 , H01L21/561 , H01L23/28 , H01L23/29 , H01L23/3114 , H01L23/481 , H01L23/50 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L2224/02379 , H01L2224/03462 , H01L2224/0348 , H01L2224/03903 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05541 , H01L2224/05569 , H01L2224/05571 , H01L2224/05647 , H01L2224/0603 , H01L2224/11422 , H01L2224/13111 , H01L2224/16145 , H01L2224/94 , H01L2225/06513 , H01L2225/06548 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2224/03 , H01L2224/11 , H01L2924/00012 , H01L2924/01047 , H01L2224/05552
摘要： Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.
摘要翻译： 描述了诸如晶片级封装半导体器件的半导体封装器件，其具有用于提供电互连性的柱。 在一个实现中，晶片级封装器件包括集成电路芯片，其具有形成在集成电路芯片上的至少一个柱。 支柱被配置为提供与集成电路芯片的电互连性。 晶片级封装器件还包括被配置为支撑柱的封装结构。
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公开(公告)号：US08860222B2
公开(公告)日：2014-10-14
申请号：US13690634
申请日：2012-11-30
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L25/065 , H01L23/00 , H01L21/56 , H01L23/29 , H01L23/31 , H01L23/50
CPC分类号： H01L21/76877 , H01L21/56 , H01L21/561 , H01L23/28 , H01L23/29 , H01L23/3114 , H01L23/481 , H01L23/50 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L2224/02379 , H01L2224/03462 , H01L2224/0348 , H01L2224/03903 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05541 , H01L2224/05569 , H01L2224/05571 , H01L2224/05647 , H01L2224/0603 , H01L2224/11422 , H01L2224/13111 , H01L2224/16145 , H01L2224/94 , H01L2225/06513 , H01L2225/06548 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2224/03 , H01L2224/11 , H01L2924/00012 , H01L2924/01047 , H01L2224/05552
摘要： Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.
摘要翻译： 描述了诸如晶片级封装半导体器件的半导体封装器件，其具有用于提供电互连性的柱。 在一个实现中，晶片级封装器件包括集成电路芯片，其具有形成在集成电路芯片上的至少一个柱。 支柱被配置为提供与集成电路芯片的电互连性。 晶片级封装器件还包括被配置为支撑柱的封装结构。
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公开(公告)号：US20140264845A1
公开(公告)日：2014-09-18
申请号：US13930788
申请日：2013-06-28
发明人： Amit S. Kelkar , Viren Khandekar , Hien D. Nguyen
IPC分类号： H01L23/00
CPC分类号： H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/11312 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/11436 , H01L2224/1145 , H01L2224/1146 , H01L2224/11462 , H01L2224/1182 , H01L2224/11849 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2224/13564 , H01L2224/136 , H01L2224/16145 , H01L2224/16225 , H01L2224/2919 , H01L2224/32145 , H01L2224/73103 , H01L2224/73204 , H01L2224/81815 , H01L2224/83191 , H01L2224/8385 , H01L2224/83851 , H01L2224/92242 , H01L2225/06513 , H01L2225/06541 , H01L2924/351 , H01L2924/00014 , H01L2924/014 , H01L2924/01047 , H01L2924/01029 , H01L2924/00012 , H01L2924/0665 , H01L2224/11 , H01L2924/00
摘要： A wafer-level package device and techniques for fabricating the device are described that include a second integrated circuit chip electrically coupled to a base integrated circuit chip, where the second integrated circuit chip is placed on and connected to the base integrated circuit chip between multiple high-standoff peripheral pillars with solder bumps. In implementations, the wafer-level package device that employs example techniques in accordance with the present disclosure includes a base integrated circuit chip, multiple high-standoff peripheral pillars with solder bumps, and a second integrated circuit chip electrically coupled to the base integrated circuit chip and placed on the base integrated circuit chip in the center of an array of high-standoff peripheral pillars with solder bumps.
摘要翻译： 描述了晶片级封装器件和用于制造器件的技术，其包括电耦合到基极集成电路芯片的第二集成电路芯片，其中第二集成电路芯片放置在多个高电平之间并连接到基极集成电路芯片 - 具有焊料凸块的外围柱。 在实现中，采用根据本公开的示例技术的晶片级封装器件包括基极集成电路芯片，具有焊料凸块的多个高间隔外围柱和与基极集成电路芯片电耦合的第二集成电路芯片 并放置在具有焊料凸块的高间隔外围柱阵列的中心的基底集成电路芯片上。
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公开(公告)号：US20130161817A1
公开(公告)日：2013-06-27
申请号：US13690634
申请日：2012-11-30
CPC分类号： H01L21/76877 , H01L21/56 , H01L21/561 , H01L23/28 , H01L23/29 , H01L23/3114 , H01L23/481 , H01L23/50 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L2224/02379 , H01L2224/03462 , H01L2224/0348 , H01L2224/03903 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05541 , H01L2224/05569 , H01L2224/05571 , H01L2224/05647 , H01L2224/0603 , H01L2224/11422 , H01L2224/13111 , H01L2224/16145 , H01L2224/94 , H01L2225/06513 , H01L2225/06548 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2224/03 , H01L2224/11 , H01L2924/00012 , H01L2924/01047 , H01L2224/05552
摘要： Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.
摘要翻译： 描述了诸如晶片级封装半导体器件的半导体封装器件，其具有用于提供电互连性的柱。 在一个实现中，晶片级封装器件包括集成电路芯片，其具有形成在集成电路芯片上的至少一个柱。 支柱被配置为提供与集成电路芯片的电互连性。 晶片级封装器件还包括被配置为支撑柱的封装结构。
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公开(公告)号：US20160071826A1
公开(公告)日：2016-03-10
申请号：US14942708
申请日：2015-11-16
IPC分类号： H01L25/065 , H01L25/00
CPC分类号： H01L25/0657 , H01L21/561 , H01L23/3121 , H01L23/5389 , H01L24/16 , H01L24/19 , H01L24/24 , H01L24/25 , H01L24/73 , H01L25/50 , H01L2224/02371 , H01L2224/0239 , H01L2224/0401 , H01L2224/05548 , H01L2224/12105 , H01L2224/13024 , H01L2224/131 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/24146 , H01L2224/24226 , H01L2224/25171 , H01L2224/32145 , H01L2224/73209 , H01L2224/73253 , H01L2224/73267 , H01L2224/94 , H01L2224/96 , H01L2224/97 , H01L2225/06513 , H01L2225/06524 , H01L2225/06548 , H01L2225/06558 , H01L2225/06586 , H01L2225/06589 , H01L2924/01029 , H01L2924/10253 , H01L2924/1461 , H01L2924/181 , H01L2924/3511 , H01L2224/11 , H01L2924/00014 , H01L2924/01079 , H01L2224/81 , H01L2924/00 , H01L2924/014
摘要： An integrated circuit device is disclosed that includes a semiconductor substrate and a die attached to the semiconductor substrate. A conductive pillar is connected to at least one of the semiconductor substrate or the die. An overmold is molded onto the semiconductor substrate over the die, and the conductive pillar extends through the overmold.
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7.发明授权公开(公告)号：US09219043B2
公开(公告)日：2015-12-22
申请号：US13930788
申请日：2013-06-28
发明人： Amit S. Kelkar , Viren Khandekar , Hien D. Nguyen
CPC分类号： H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/11312 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/11436 , H01L2224/1145 , H01L2224/1146 , H01L2224/11462 , H01L2224/1182 , H01L2224/11849 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2224/13564 , H01L2224/136 , H01L2224/16145 , H01L2224/16225 , H01L2224/2919 , H01L2224/32145 , H01L2224/73103 , H01L2224/73204 , H01L2224/81815 , H01L2224/83191 , H01L2224/8385 , H01L2224/83851 , H01L2224/92242 , H01L2225/06513 , H01L2225/06541 , H01L2924/351 , H01L2924/00014 , H01L2924/014 , H01L2924/01047 , H01L2924/01029 , H01L2924/00012 , H01L2924/0665 , H01L2224/11 , H01L2924/00
摘要： A wafer-level package device and techniques for fabricating the device are described that include a second integrated circuit chip electrically coupled to a base integrated circuit chip, where the second integrated circuit chip is placed on and connected to the base integrated circuit chip between multiple high-standoff peripheral pillars with solder bumps. In implementations, the wafer-level package device that employs example techniques in accordance with the present disclosure includes a base integrated circuit chip, multiple high-standoff peripheral pillars with solder bumps, and a second integrated circuit chip electrically coupled to the base integrated circuit chip and placed on the base integrated circuit chip in the center of an array of high-standoff peripheral pillars with solder bumps.
摘要翻译： 描述了晶片级封装器件和用于制造器件的技术，其包括电耦合到基极集成电路芯片的第二集成电路芯片，其中第二集成电路芯片放置在多个高电平之间并连接到基极集成电路芯片 - 具有焊料凸块的外围柱。 在实现中，采用根据本公开的示例技术的晶片级封装器件包括基极集成电路芯片，具有焊料凸块的多个高间隔外围柱和与基极集成电路芯片电耦合的第二集成电路芯片 并放置在具有焊料凸块的高间隔外围柱阵列的中心的基底集成电路芯片上。
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公开(公告)号：US20150028475A1
公开(公告)日：2015-01-29
申请号：US14512506
申请日：2014-10-13
IPC分类号： H01L21/768 , H01L23/28 , H01L23/48 , H01L21/56 , H01L23/00
CPC分类号： H01L21/76877 , H01L21/56 , H01L21/561 , H01L23/28 , H01L23/29 , H01L23/3114 , H01L23/481 , H01L23/50 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L2224/02379 , H01L2224/03462 , H01L2224/0348 , H01L2224/03903 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05541 , H01L2224/05569 , H01L2224/05571 , H01L2224/05647 , H01L2224/0603 , H01L2224/11422 , H01L2224/13111 , H01L2224/16145 , H01L2224/94 , H01L2225/06513 , H01L2225/06548 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2224/03 , H01L2224/11 , H01L2924/00012 , H01L2924/01047 , H01L2224/05552
摘要： Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.
摘要翻译： 描述了诸如晶片级封装半导体器件的半导体封装器件，其具有用于提供电互连性的柱。 在一个实现中，晶片级封装器件包括集成电路芯片，其具有形成在集成电路芯片上的至少一个柱。 支柱被配置为提供与集成电路芯片的电互连性。 晶片级封装器件还包括被配置为支撑柱的封装结构。
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