公开(公告)号：US10032749B2

公开(公告)日：2018-07-24

申请号：US14942708

申请日：2015-11-16

申请人： Maxim Integrated Products, Inc.

发明人： Amit S. Kelkar ,  Karthik Thambidurai ,  Viren Khandekar ,  Hien D. Nguyen

IPC分类号： H01L21/00 ,  H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56

摘要： An integrated circuit device is disclosed that includes a semiconductor substrate and a die attached to the semiconductor substrate. A conductive pillar is connected to at least one of the semiconductor substrate or the die. An overmold is molded onto the semiconductor substrate over the die, and the conductive pillar extends through the overmold.

公开(公告)号：US20150325512A1

公开(公告)日：2015-11-12

申请号：US14803612

申请日：2015-07-20

申请人： Maxim Integrated Products, Inc.

发明人： Arkadii V. Samoilov ,  Peter R. Harper ,  Viren Khandekar ,  Pirooz Parvarandeh

IPC分类号： H01L23/498 ,  H01L21/311 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L23/49838 ,  H01L21/311 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/563 ,  H01L23/28 ,  H01L23/3107 ,  H01L24/81 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1515 ,  H01L2924/00 ,  H01L2224/03

摘要： Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts.

摘要翻译： 描述了用于高电流应用的晶片级封装半导体器件，其具有用于提供电互连性的柱。 在一个实现中，晶片级封装器件包括集成电路芯片，其具有形成在集成电路芯片上的至少一个柱。 支柱被配置为提供与集成电路芯片的电互连性。 晶片级封装器件还包括被配置为支撑柱的封装结构。 晶片级封装器件还包括在集成电路芯片（例如，大裸片）上配置的集成电路芯片器件（例如，小芯片）。 在晶片级封装器件中，集成电路芯片器件的高度小于柱的高度和/或小于柱和一个或多个焊接触点的组合高度。

公开(公告)号：US20140131859A1

公开(公告)日：2014-05-15

申请号：US13929978

申请日：2013-06-28

申请人： Maxim Integrated Products, Inc.

发明人： Yong Li Xu ,  Tiao Zhou ,  Xiansong Chen ,  Kaysar M. Rahim ,  Viren Khandekar ,  Yi-Sheng Anthony Sun ,  Arkadii V. Samoilov

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L23/49811 ,  H01L21/76885 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02165 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05541 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05563 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/05578 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/10125 ,  H01L2224/13013 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1416 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26125 ,  H01L2224/29013 ,  H01L2224/32227 ,  H01L2224/3303 ,  H01L2224/33051 ,  H01L2224/3316 ,  H01L2224/81192 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83365 ,  H01L2224/83815 ,  H01L2924/351 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

摘要： A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

摘要翻译： 晶片级封装包括晶片，用于将晶片连接到电路的晶片设置的引线和设置在引线上的芯。 在一些实施例中，设置晶片的引线是铜柱，并且芯被镀在铜柱上。 在一些实施方案中，芯是聚合物丝网电镀到引线上。 在一些实施例中，芯从引线延伸至少约35微米（35微米）和50微米（50μm）。 在一些实施例中，芯覆盖在铅的表面积的至少约三分之一（1/3）和一半（1/2）之间。 在一些实施例中，芯包括从引线延伸的螺柱形状。 在一些实施例中，芯垂直延伸穿过导线。 在一些实施例中，芯沿着引线纵向延伸。 此外，芯的一部分可以从纵向芯垂直延伸。

公开(公告)号：US11428735B1

公开(公告)日：2022-08-30

申请号：US16817564

申请日：2020-03-12

申请人： Maxim Integrated Products, Inc.

发明人： Ruel Jucoy Mijares ,  Viren Khandekar ,  Edson Macgregor Arca Leano ,  Hilario Sanchez Jacala

IPC分类号： G01R31/30 ,  G01R31/307 ,  G01R1/04

摘要： A system for monitoring and controlling an IC testing machine includes a vibration sensor, a sensor interface, and a processor coupled to the sensor interface. The vibration sensor is in mechanical communication with an IC testing machine to develop an electrical vibration signal representing mechanical vibrations generated by the operation of the IC testing machine. The sensor interface processes the vibration signal to develop vibration data that can be processed by the processor to determine whether the vibration data is indicative of an operational anomaly and, if so, to generate a machine control signal to correct an operation of the IC testing machine. Multiple vibration sensors can be used to increase the amount of vibration data available for analysis.

公开(公告)号：US09583425B2

公开(公告)日：2017-02-28

申请号：US13929978

申请日：2013-06-28

申请人： Maxim Integrated Products, Inc.

发明人： Yong Li Xu ,  Tiao Zhou ,  Xiansong Chen ,  Kaysar M. Rahim ,  Viren Khandekar ,  Yi-Sheng Anthony Sun ,  Arkadii V. Samoilov

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L21/768

CPC分类号： H01L23/49811 ,  H01L21/76885 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02165 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05541 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05563 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/05578 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/10125 ,  H01L2224/13013 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1416 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26125 ,  H01L2224/29013 ,  H01L2224/32227 ,  H01L2224/3303 ,  H01L2224/33051 ,  H01L2224/3316 ,  H01L2224/81192 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83365 ,  H01L2224/83815 ,  H01L2924/351 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

摘要： A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

摘要翻译： 晶片级封装包括晶片，用于将晶片连接到电路的晶片设置的引线和设置在引线上的芯。 在一些实施例中，设置晶片的引线是铜柱，并且芯被镀在铜柱上。 在一些实施方案中，芯是聚合物丝网电镀到引线上。 在一些实施例中，芯从引线延伸至少约35微米（35微米）和50微米（50μm）。 在一些实施例中，芯覆盖在铅的表面积的至少约三分之一（1/3）和一半（1/2）之间。 在一些实施例中，芯包括从引线延伸的螺柱形状。 在一些实施例中，芯垂直延伸穿过导线。 在一些实施例中，芯沿着引线纵向延伸。 此外，芯的一部分可以从纵向芯垂直延伸。

公开(公告)号：US09230903B2

公开(公告)日：2016-01-05

申请号：US14803612

申请日：2015-07-20

申请人： Maxim Integrated Products, Inc.

发明人： Arkadii V. Samoilov ,  Peter R. Harper ,  Viren Khandekar ,  Pirooz Parvarandeh

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/311

CPC分类号： H01L23/49838 ,  H01L21/311 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/563 ,  H01L23/28 ,  H01L23/3107 ,  H01L24/81 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1515 ,  H01L2924/00 ,  H01L2224/03

摘要： Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts.

公开(公告)号：US09087779B2

公开(公告)日：2015-07-21

申请号：US13732664

申请日：2013-01-02

申请人： Maxim Integrated Products, Inc.

发明人： Arkadii V. Samoilov ,  Peter R. Harper ,  Viren Khandekar ,  Pirooz Parvarandeh

IPC分类号： H01L23/28 ,  H01L21/56

CPC分类号： H01L23/49838 ,  H01L21/311 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/563 ,  H01L23/28 ,  H01L23/3107 ,  H01L24/81 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1515 ,  H01L2924/00 ,  H01L2224/03

摘要： Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts.

摘要翻译： 描述了用于高电流应用的晶片级封装半导体器件，其具有用于提供电互连性的柱。 在一个实现中，晶片级封装器件包括集成电路芯片，其具有形成在集成电路芯片上的至少一个柱。 支柱被配置为提供与集成电路芯片的电互连性。 晶片级封装器件还包括被配置为支撑柱的封装结构。 晶片级封装器件还包括在集成电路芯片（例如，大裸片）上配置的集成电路芯片器件（例如，小芯片）。 在晶片级封装器件中，集成电路芯片器件的高度小于柱的高度和/或小于柱和一个或多个焊接触点的组合高度。

公开(公告)号：US20140264845A1

公开(公告)日：2014-09-18

申请号：US13930788

申请日：2013-06-28

申请人： MAXIM INTEGRATED PRODUCTS, INC.

发明人： Amit S. Kelkar ,  Viren Khandekar ,  Hien D. Nguyen

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11436 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1182 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/136 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/92242 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/11 ,  H01L2924/00

摘要： A wafer-level package device and techniques for fabricating the device are described that include a second integrated circuit chip electrically coupled to a base integrated circuit chip, where the second integrated circuit chip is placed on and connected to the base integrated circuit chip between multiple high-standoff peripheral pillars with solder bumps. In implementations, the wafer-level package device that employs example techniques in accordance with the present disclosure includes a base integrated circuit chip, multiple high-standoff peripheral pillars with solder bumps, and a second integrated circuit chip electrically coupled to the base integrated circuit chip and placed on the base integrated circuit chip in the center of an array of high-standoff peripheral pillars with solder bumps.

摘要翻译： 描述了晶片级封装器件和用于制造器件的技术，其包括电耦合到基极集成电路芯片的第二集成电路芯片，其中第二集成电路芯片放置在多个高电平之间并连接到基极集成电路芯片 - 具有焊料凸块的外围柱。 在实现中，采用根据本公开的示例技术的晶片级封装器件包括基极集成电路芯片，具有焊料凸块的多个高间隔外围柱和与基极集成电路芯片电耦合的第二集成电路芯片 并放置在具有焊料凸块的高间隔外围柱阵列的中心的基底集成电路芯片上。

公开(公告)号：US20130161817A1

公开(公告)日：2013-06-27

申请号：US13690634

申请日：2012-11-30

申请人： Maxim Integrated Products, Inc.

发明人： Viren Khandekar ,  Karthik Thambidurai ,  Ahmad Ashrafzadeh ,  Amit Kelkar ,  Hien D. Nguyen

IPC分类号： H01L23/29 ,  H01L23/50 ,  H01L21/56

CPC分类号： H01L21/76877 ,  H01L21/56 ,  H01L21/561 ,  H01L23/28 ,  H01L23/29 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/50 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/02379 ,  H01L2224/03462 ,  H01L2224/0348 ,  H01L2224/03903 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05541 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/11422 ,  H01L2224/13111 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2224/05552

摘要： Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.

摘要翻译： 描述了诸如晶片级封装半导体器件的半导体封装器件，其具有用于提供电互连性的柱。 在一个实现中，晶片级封装器件包括集成电路芯片，其具有形成在集成电路芯片上的至少一个柱。 支柱被配置为提供与集成电路芯片的电互连性。 晶片级封装器件还包括被配置为支撑柱的封装结构。

公开(公告)号：US09087732B1

公开(公告)日：2015-07-21

申请号：US14170824

申请日：2014-02-03

申请人： Maxim Integrated Products, Inc.

发明人： Yong L. Xu ,  Viren Khandekar ,  Yi-Sheng A. Sun ,  Arkadii V. Samoilov

IPC分类号： H01L21/44 ,  H01L23/00

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0239 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05172 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05563 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05672 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/1401 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14179 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2224/05552

摘要： Wafer-level package (semiconductor) devices are described that have a pillar structure that extends at least partially into a solder bump to mitigate thermal stresses to the solder bump. In implementations, the wafer-level package device may comprise an integrated circuit chip having a surface and a solder bump disposed over the surface. The wafer-level package device may also include a pillar structure disposed over the surface that extends at least partially into the solder bump.

摘要翻译： 描述了晶片级封装（半导体）器件，其具有至少部分地延伸到焊料凸块中以减轻对焊料凸块的热应力的柱结构。 在实现中，晶片级封装器件可以包括具有设置在表面上的表面和焊料凸块的集成电路芯片。 晶片级封装器件还可以包括设置在表面上的至少部分地延伸到焊料凸块中的柱结构。