摘要:
A thin-film bypass capacitor is fabricated by forming a plurality of through holes through the thickness of a nonconductive base substrate and filling the through holes with a conductive material to form ground vias and power vias. A sequence of back side metalization layers are applied to the back side surface of the base substrate. A sequence of bottom contact layers are applied to the front side surface of the base substrate. A bottom contact power terminal is formed and a bottom contact metalization layer is applied to the surface of the bottom contact layers. A portion of the metalization layer is removed and an insulating layer is formed on the surface of the bottom contact metalization layer. A ground metalization feedthrough and a power metalization feedthrough are formed at the surface of the insulating layer. A sequence of top contact layers are applied to the surface of the insulating layer and a front side ground terminal and front side power terminal are formed. A back side ground terminal and a back side power terminal are formed at the back side of the base substrate.
摘要:
A thin-film bypass capacitor is fabricated by forming a plurality of through holes through the thickness of a nonconductive base substrate and filling the through holes with a conductive material to form ground vias and power vias. A sequence of back side metalization layers are applied to the back side surface of the base substrate. A sequence of bottom contact layers are applied to the front side surface of the base substrate. A bottom contact power terminal is formed and a bottom contact metalization layer is applied to the surface of the bottom contact layers. A portion of the metalization layer is removed and an insulating layer is formed on the surface of the bottom contact metalization layer. A ground metalization feedthrough and a power metalization feedthrough are formed at the surface of the insulating layer. A sequence of top contact layers are applied to the surface of the insulating layer and a front side ground terminal and front side power terminal are formed. A back side ground terminal and a back side power terminal are formed at the back side of the base substrate.
摘要:
A multichip module substrate for use in a three-dimensional multichip module, and methods of making the same, are disclosed. The substrate comprises a thin film structure, for routing signals to and from integrated circuit chips, formed over a rigid support base. Apertures are formed in the support base exposing the underside of the thin film structure, thereby allowing high density connectors to be mounted on both surfaces of the thin film structure, greatly enhancing the ability to communicate signals between adjacent substrates in the chip module. This avoids the need to route the signals either through the rigid support base or to the edges of the thin film structure. Power and ground, which do not require a high connection density, are routed in low impedance paths through the support base. Preferably, the thin film structure is made of alternating layers of patterned metal, such as copper, and a low dielectric organic polymer, such as a polyimide.
摘要:
A three dimensional thin-film interconnector is fabricated by depositing a dielectric layer onto the surface of a substrate, depositing a layer of conductive material onto the dielectric layer to form a signal plane, depositing a dielectric layer onto the surface of the signal plane, forming a plurality of through holes in the dielectric layer that extend to the signal plane, and filling the through holes with an electrically conductive material to form vias. The sequence of forming a signal plane, depositing a dielectric layer, forming a plurality of through holes, and filling the through holes is repeated until a predetermined number of signal planes and a predetermined arrangement of vias are obtained. The through holes are formed at locations in the dielectric layers corresponding to both predetermined electrical connections and the vias in a preceding dielectric layer. The signal planes are formed at different locations on the substrate. The sequence of signal planes and dielectric layers at the same location on the substrate form a signal plane set which defines a connector. Contact pads are deposited onto the surface of a final dielectric layer and electrically connect with each via. Wires are used to electrically connect the contact pads of one connector to corresponding contact pads of another connector. A portion of the substrate and dielectric layers not comprising a signal plane set is removed, forming electrical connectors flexibly attached by the plurality of wires.
摘要:
A high density through-hole interconnect with high aspect ratio vias is formed by sequentially forming layers of dielectric material on a previous dielectric layer. After each layer is formed, a plurality of through holes are etched through each layer and filled or metalized with an electrically conductive material having a coefficient of thermal expansion matching that of the dielectric layers and the integrated circuit that it will connect with. Preferably, the process of forming dielectric layers, forming through holes, and metalizing the through holes is repeated until the metalized through holes have an aspect ratio in the range of from 6 to 10. A support structure is constructed to interconnect with and support the metalized vias while the dielectric material is removed. A second dielectric material having the desired mechanical and electrical properties is poured into the support structure to fill the space between the metalized vias and allowed to solidify. The support structure is removed and the through-hole interconnector, comprising the metalized vias and the second dielectric material, is lapped and polished to predetermined manufacturing dimensions and tolerances.
摘要:
A method of curing an organic dielectric layer, such as polyimide, used in a multichip module is disclosed. The method comprises heating the uncured polyimide layer to a temperature above its glass transition temperature, and irradiating the layer with a uniform flux of electrons, as in an e-beam apparatus. The process reduces deterioration at the interface between the dielectric films and the metal layers which when high temperature thermal curing is utilized, and reduces the stress of the resulting film. Multiple dielectric layers can be applied in this manner.
摘要:
A thin-film bypass capacitor is fabricated by forming a plurality of through holes through the thickness of a nonconductive base substrate and filling the through holes with a conductive material to form ground vias and power vias. A sequence of back side metalization layers are applied to the back side surface of the base substrate. A sequence of bottom contact layers are applied to the front side surface of the base substrate. A bottom contact power terminal is formed in the bottom contact layer and is electrically isolated from remaining portions of the bottom contact layers by insulating plugs. A bottom contact metalization layer is applied to the surface of the bottom contact layers and the insulating plugs. A dielectric layer is formed on the surface of the bottom contact metalization layer. A ground metalization via and a power metalization via are formed at the surface of the dielectric layer. A sequence of top contact layers are applied to the surface of the dielectric layer and a front side ground terminal and front side power terminal are formed. A back side ground terminal and a back side power terminal are formed at the back side of the base substrate.
摘要:
Interconnect carriers for coupling integrated circuit chips to major substrates and methods for making the same are disclosed. The interconnect carrier comprises a relatively thin resilient supporting layer, a plurality of electrically conductive vias formed through the surfaces of the supporting layer, and an outer frame disposed around the periphery of the supporting layer. The supporting layer preferably comprises an electrically insulating material. The flexibility of the supporting layer enables the layer to more readily conform to the warpages of the IC chip and supporting substrate, while the outer frame provides mechanical support and prevents the supporting layer from folding, twisting, and/or stretching. The thickness of the supporting layer may be substantially reduced over that of prior art interposers to enable methods for constructing smaller diameter vias.
摘要:
A semiconductor chip carrier has a first substrate and at least one second substrate. The first substrate is for carrying at least one semiconductor chip of integrated circuits. The first substrate has predetermined functional elements for connection to the integrated circuits of the at least one semiconductor chip. Such a second substrate is directly coupled to the first substrate. The second substrate is capable of being independently created and has predetermined electrical functional elements for connection to the integrated circuits of the semiconductor chip. The electrical functional elements of each second substrate are of one type and are different than the electrical functional elements of the other second substrates and the first substrate.The second substrate has a top interconnect layer, a bottom interconnect layer, and a plurality of intra-substrate connectors (or through-hole connectors), where the top interconnect layer and the bottom interconnect layer have substantially identical patterns of electrical contacts. The electrical contacts may be deformable bumps, solder bumps, elastomer bumps, or gold bumps.The electrical functional elements are electrically passive circuits, such as capacitors, resistors, or electrical signal conductors. Such a second substrate may include power supply circuits.
摘要:
A semiconductor device is manufactured by subdividing the chip carrier into a plurality of functional substrates, such as a signal connection substrate, a capacitor substrate, a resistor substrate and a power supply substrate. The several substrates are individually manufactured and tested before they are assembled. Advantageously, the manufacturing and testing of the substrates are carried out in parallel, so as to reduce manufacturing time of the semiconductor device.Each substrate has a top interconnect layer and a bottom interconnect layer. Each interconnect layer has a plurality of bond pads in an identical pattern. The pads are formed using the same design rules, structure, pitch, diameter and fabrication process for each layer. This identity allows the different functional substrates to be electrically interchanged without changing the interconnection layers. Although changes internal in the substrate may be required.