公开(公告)号：US4826781A

公开(公告)日：1989-05-02

申请号：US21055

申请日：1987-03-02

申请人： Michio Asahina ,  Makio Goto

发明人： Michio Asahina ,  Makio Goto

IPC分类号： H01L21/308 ,  H01L21/336 ,  H01L21/60 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/04 ,  H01L21/265

CPC分类号： H01L27/10861 ,  H01L21/3086 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/76897 ,  H01L27/04 ,  H01L29/66636 ,  Y10S257/90

摘要： A method for preparing an improved semiconductor device having a transistor and a capacitor or an element isolating region in or on a semiconductor substrate by a self-alignment process is provided. Each of the elements is formed using a previously formed element as a mask so that no additional processes are necessary to align the elements at the desired position. Specifically, a gate electrode is formed first and then a capacitor, element isolating region and contact hole are formed in such a way that the room required for alignment of the gate electrode and the capacitor, the gate electrode and the element isolating region and the gate electrode and the contact hole is reduced. The process is extremely advantageous for miniaturization of the semiconductor device. The device prepared by such a process is also provided.

摘要翻译： 提供一种通过自对准方法制备具有晶体管和电容器或元件隔离区域的半导体器件的半导体器件的方法。 使用先前形成的元件作为掩模形成每个元件，使得不需要额外的处理来将元件对准在期望的位置。 具体地，首先形成栅电极，然后形成电容器，元件隔离区域和接触孔，使得栅电极和电容器，栅极电极和元件隔离区域和栅极对准所需的室 电极和接触孔减少。 该方法非常有利于半导体器件的小型化。 还提供了通过这种方法制备的装置。

公开(公告)号：US06350685B1

公开(公告)日：2002-02-26

申请号：US09412200

申请日：1999-10-05

申请人： Michio Asahina ,  Eiji Suzuki ,  Kazuki Matsumoto ,  Naohiro Moriya

发明人： Michio Asahina ,  Eiji Suzuki ,  Kazuki Matsumoto ,  Naohiro Moriya

IPC分类号： H01L2144

CPC分类号： H01L21/76846 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76888

摘要： A semiconductor device is manufactured by a method including the steps of forming a through hole in an interlayer dielectric layer (silicon oxide layer, BPSG layer, etc.) formed on a semiconductor substrate having a device element. A barrier layer is formed on surfaces of the interlayer dielectric layer and the through hole. A wiring layer is formed on the barrier layer. The barrier layer is formed by a method including the following steps. A titanium layer that forms at least a part of the barrier layer is formed. A heat treatment is conducted in a nitrogen atmosphere to form a titanium nitride layer at least on a surface of the titanium layer. The titanium nitride layer is contacted with oxygen in an atmosphere including oxygen. A heat treatment is conducted in a nitrogen atmosphere to form titanium oxide layers and to densify the titanium nitride layer.

摘要翻译： 通过包括在形成有具有器件元件的半导体衬底上的层间电介质层（氧化硅层，BPSG层等）中形成通孔的方法制造半导体器件。 在层间电介质层和通孔的表面上形成阻挡层。 在阻挡层上形成布线层。 通过包括以下步骤的方法形成阻挡层。 形成形成阻挡层的至少一部分的钛层。 在氮气气氛中进行热处理，至少在钛层的表面上形成氮化钛层。 氮化钛层在包含氧的气​​氛中与氧接触。 在氮气气氛中进行热处理以形成氧化钛层并致密化氮化钛层。

公开(公告)号：US06194304B1

公开(公告)日：2001-02-27

申请号：US09300378

申请日：1999-04-27

申请人： Yukio Morozumi ,  Michio Asahina ,  Naohiro Moriya ,  Kazuki Matsumoto ,  Eiji Suzuki

发明人： Yukio Morozumi ,  Michio Asahina ,  Naohiro Moriya ,  Kazuki Matsumoto ,  Eiji Suzuki

IPC分类号： H01L2144

CPC分类号： H01L21/76828 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31051 ,  H01L21/31625 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process of forming an interlayer dielectric on a semiconductor substrate including an electronic element comprises at least the following steps (a) to (c): (a) a step of forming a first silicon oxide layer by reacting a silicon compound including hydrogen with hydrogen peroxide using a chemical vapor deposition method; (b) a step of forming a porous second silicon oxide layer by reacting between a compound including an impurity, silicon compounds, and at least one substance selected from oxygen and compounds including oxygen using a chemical vapor deposition method; and (c) a step of annealing at a temperature of 300° C. to 850° C. to make the first and second silicon oxide layers more fine-grained. The first silicon oxide layer is formed at a temperature that is lower than that required for a BPSG film, and it has superior self-flattening characteristics in itself.

摘要翻译： 在包括电子元件的半导体衬底上形成层间电介质的工艺至少包括以下步骤（a）至（c）：（a）通过使包含氢的硅化合物与氢反应形成第一氧化硅层的步骤 使用化学气相沉积方法的过氧化物;（b）通过使用化学气相沉积法在包括杂质，硅化合物和至少一种选自氧的化合物和包括氧的化合物中的化合物之间反应形成多孔的第二氧化硅层的步骤 方法; 和（c）在300℃至850℃的温度下退火的步骤，以使第一和第二氧化硅层更细粒化。第一氧化硅层形成在低于该温度的温度 BPSG膜所需的，它本身具有优异的自扁平特性。

公开(公告)号：US06107182A

公开(公告)日：2000-08-22

申请号：US161920

申请日：1998-09-29

申请人： Michio Asahina ,  Junichi Takeuchi ,  Naohiro Moriya ,  Kazuki Matsumoto

发明人： Michio Asahina ,  Junichi Takeuchi ,  Naohiro Moriya ,  Kazuki Matsumoto

IPC分类号： H01L21/203 ,  H01L21/285 ,  H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76814 ,  H01L21/28518 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76877

摘要： A semiconductor device having a contact structure that can exhibit superlative step coverage without causing voids or wiring discontinuities, using aluminum or aluminum alloys as a conductive substance for via-holes. A method of fabricating the semiconductor device comprises, for at least one layer of wiring regions above the first wiring region on a semiconductor substrate, the following steps (a) to (f): (a) a step of forming a via-hole in a second interlayer dielectric formed above the first wiring region on a semiconductor substrate; (b) a degassing step for removing gaseous components included within the interlayer dielectric by a heat treatment under reduced pressure and at the substrate temperature of 300.degree. C. to 550.degree. C.; (c) a step of forming a wetting layer on the surface of the interlayer dielectric and the via-hole; (d) a step of cooling the substrate to a temperature of no more than 100.degree. C.; (e) a step of forming a first aluminum layer comprising one of aluminum and an alloy in which aluminum is the main component on the wetting layer at a temperature of no more than 200.degree. C.; and (f) a step of forming a second aluminum layer comprising one of aluminum and an alloy in which aluminum is the main component on the first aluminum layer at a temperature of at least 300.degree. C.

摘要翻译： 一种具有接触结构的半导体器件，其可以显示出最高级的覆盖范围，而不引起空隙或接线不连续性，使用铝或铝合金作为通孔的导电物质。 制造半导体器件的方法包括：对于在半导体衬底上的第一布线区域上方的至少一层布线区域，以下步骤（a）至（f）：（a）形成通孔的步骤 形成在半导体衬底上的第一布线区域上方的第二层间电介质; （b）通过减压热处理和基板温度在300℃至550℃除去层间电介质中包含的气体组分的脱气步骤。 （c）在层间电介质和通孔的表面上形成润湿层的步骤; （d）将基板冷却至不超过100℃的温度; （e）在不超过200℃的温度下形成包含铝和合金中的铝的第一铝层的步骤，其中铝是润湿层上的主要成分。 和（f）在至少300℃的温度下形成第一铝层的步骤，所述第二铝层包括铝和合金中的一种，其中铝是第一铝层上的主要成分。

公开(公告)号：US5093276A

公开(公告)日：1992-03-03

申请号：US702134

申请日：1991-05-13

申请人： Michio Asahina

发明人： Michio Asahina

IPC分类号： H01L21/8238 ,  H01L23/532 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L27/0928 ,  H01L21/823835 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/53271 ,  H01L2924/0002

摘要： A novel semiconductor device and method of production of such a device are provided. Both the N and P channels of the novel semiconductor device are formed by contact self-alignment, thereby permitting high speed operation and high density integration to be realized. The formation of the channels by contact self-alignment is accomplished by depositing a P type polysilicon layer on an N well region and an N type polysilicon layer on a P well region. A silicide layer is formed over both the P and N type polysilicon layers to form a polycide.

公开(公告)号：US06812123B2

公开(公告)日：2004-11-02

申请号：US09818743

申请日：2001-03-27

申请人： Kazuki Matsumoto ,  Yukio Morozumi ,  Michio Asahina

发明人： Kazuki Matsumoto ,  Yukio Morozumi ,  Michio Asahina

IPC分类号： H01L2144

CPC分类号： H01L24/48 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05179 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/451 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/05341 ,  H01L2924/12043 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/04953 ,  H01L2224/45099 ,  H01L2924/00

摘要： Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The interlayer dielectric layer 20 includes at least a first silicon oxide layer 20b that is formed by a polycondensation reaction of a silicon compound and hydrogen peroxide, and a second silicon oxide layer 20c formed over the first silicon oxide layer and containing an impurity. The pad section 30A includes a wetting layer 32, an alloy layer 34 and a metal wiring layer 37.

摘要翻译： 本发明的某些实施例涉及一种半导体器件，其具有与层间介质层具有优异相干性的焊盘部分及其制造方法。 半导体器件1000具有在层间电介质层20上形成的焊盘层30A。层间绝缘层20至少包括通过硅化合物和过氧化氢的缩聚反应形成的第一氧化硅层20b和第二硅 氧化物层20c形成在第一氧化硅层上并含有杂质。 焊盘部分30A包括润湿层32，合金层34和金属布线层37。

公开(公告)号：US06614119B1

公开(公告)日：2003-09-02

申请号：US09521771

申请日：2000-03-09

申请人： Michio Asahina ,  Junichi Takeuchi ,  Naohiro Moriya ,  Kazuki Matsumoto

发明人： Michio Asahina ,  Junichi Takeuchi ,  Naohiro Moriya ,  Kazuki Matsumoto

IPC分类号： H01L2940

CPC分类号： H01L21/76814 ,  H01L21/28518 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76877

摘要： A semiconductor device having a contact structure that can exhibit superlative step coverage without causing voids or wiring discontinuities, using aluminum or aluminum alloys as a conductive substance for via-holes. A method of fabricating the semiconductor device comprises, for at least one layer of wiring regions above the first wiring region on a semiconductor substrate, the following steps (a) to (f): (a) a step of forming a via-hole in a second interlayer dielectric formed above the first wiring region on a semiconductor substrate; (b) a degassing step for removing gaseous components included within the interlayer dielectric by a heat treatment under reduced pressure and at the substrate temperature of 300° C. to 550° C.; (c) a step of forming a wetting layer on the surface of the interlayer dielectric and the via-hole; (d) a step of cooling the substrate to a temperature of no more than 100° C.; (e) a step of forming a first aluminum layer comprising one of aluminum and an alloy in which aluminum is the main component on the wetting layer at a temperature of no more than 200° C.; and (f) a step of forming a second aluminum layer comprising one of aluminum and an alloy in which aluminum is the main component on the first aluminum layer at a temperature of at least 300° C.

摘要翻译： 一种具有接触结构的半导体器件，其可以显示出最高级的覆盖范围，而不引起空隙或接线不连续性，使用铝或铝合金作为通孔的导电物质。 制造半导体器件的方法包括：对于在半导体衬底上的第一布线区域上方的布线区域中的至少一层的以下步骤（a）至（f）：（a）形成通孔的步骤 形成在半导体衬底上的第一布线区域上方的第二层间电介质; （b）通过减压热处理和基板温度在300℃至550℃下除去层间电介质中包含的气体组分的脱气步骤; （c）在层间电介质和通孔的表面上形成润湿层的步骤; （d）将基板冷却至不超过100℃的温度; （e）在不超过200℃的温度下形成包含铝和合金中的铝的第一铝层的步骤，其中铝是润湿层上的主要成分; 以及（f）在至少300℃的温度下形成第一铝层的步骤，所述第二铝层包括铝和合金之一，其中铝是第一铝层上的主要成分。

公开(公告)号：US6144097A

公开(公告)日：2000-11-07

申请号：US220590

申请日：1998-12-28

申请人： Michio Asahina ,  Junichi Takeuchi ,  Naohiro Moriya ,  Kazuki Matsumoto

发明人： Michio Asahina ,  Junichi Takeuchi ,  Naohiro Moriya ,  Kazuki Matsumoto

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76846 ,  H01L21/76843 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S438/927

摘要： A semiconductor device comprising a semiconductor substrate including an electronic element, interlayer dielectric (silicon oxide layer and BPSG layer) formed on the semiconductor substrate, a contact hole formed in the interlayer dielectric, a barrier layer formed on the interlayer dielectric and contact hole, and a wiring layer formed on the barrier layer. In the barrier layer, metal oxide (titanium oxide) are scattered in an island-like configuration. The barrier layer is formed by depositing a layer that is used to form the barrier layer and then introducing oxygen into the layer. The step is achieved by depositing a layer for the barrier layer, exposing the layer in oxygen plasma under reduced pressure, and subjecting the layer to the thermal processing, or, alternatively by depositing a layer for the barrier layer and subjecting the layer to thermal processing in an atmosphere of oxygen. The semiconductor device of the present invention has a barrier layer with excellent barrier properties.

摘要翻译： 一种半导体器件，包括形成在半导体衬底上的电子元件，层间电介质（氧化硅层和BPSG层）的半导体衬底，形成在层间电介质中的接触孔，形成在层间电介质和接触孔上的阻挡层，以及 形成在阻挡层上的布线层。 在阻挡层中，金属氧化物（氧化钛）以岛状构造分散。 阻挡层通过沉积用于形成阻挡层然后将氧引入层中的层而形成。 该步骤通过沉积阻挡层的层，在减压下在氧等离子体中暴露层，并对该层进行热处理，或者通过沉积用于阻挡层的层并使该层进行热处理来实现 在氧气氛中。 本发明的半导体装置具有阻隔性优异的阻挡层。

公开(公告)号：US6137176A

公开(公告)日：2000-10-24

申请号：US104403

申请日：1998-06-25

申请人： Yukio Morozumi ,  Michio Asahina ,  Naohiro Moriya ,  Kazuki Matsumoto ,  Eiji Suzuki

发明人： Yukio Morozumi ,  Michio Asahina ,  Naohiro Moriya ,  Kazuki Matsumoto ,  Eiji Suzuki

IPC分类号： H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L29/78 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76828 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31051 ,  H01L21/31625 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/5329 ,  H01L2924/0002

摘要： A process of forming an interlayer dielectric on a semiconductor substrate including an electronic element includes:forming first silicon oxide layer by reacting a silicon compound including hydrogen with hydrogen peroxide using a chemical vapor deposition method;forming a porous second silicon oxide layer by reacting between a compound including an impurity, silicon compounds, and at least one substance selected from oxygen and compounds including oxygen using a chemical vapor deposition method; andannealing at a temperature of 300.degree. C. to 850.degree. C. to make the first and second silicon oxide layers more fine-grained. The first silicon oxide layer is formed at a temperature that is lower than that required of a BPSG film, and it has superior self-flattening characteristics in itself.

摘要翻译： 在包括电子元件的半导体衬底上形成层间电介质的工艺包括：通过化学气相沉积法使包括氢的硅化合物与过氧化氢反应形成第一氧化硅层; 通过使用化学气相沉积法在包括杂质，硅化合物和至少一种选自氧的化合物和包括氧的化合物中的化合物之间反应形成多孔的第二氧化硅层; 并在300℃至850℃的温度下进行退火，以使第一和第二氧化硅层更细粒度。 第一氧化硅层形成在低于BPSG膜所要求的温度下，其本身具有优异的自扁平化特性。

公开(公告)号：US5342806A

公开(公告)日：1994-08-30

申请号：US780455

申请日：1991-10-22

申请人： Michio Asahina

发明人： Michio Asahina

IPC分类号： H01L23/52 ,  C23C18/31 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L23/532 ,  H01L29/78 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L21/76838 ,  H01L21/76886 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S438/927

摘要： A semiconductor device composed of: a substrate having a doped semiconductor region, a gate wiring, a lower conductor structure, an insulating layer overlying the lower structure and having at least one through opening extending to the lower conductor structure, and an upper conductor structure connected to the lower conductor structure via the through opening, wherein at least one of the conductor structures is formed of at least one layer of a metal, a metal silicide, a metal nitride, a metal carbide or a conductive oxide film, and a metal plating layer disposed on and adhering to the at least one layer.

摘要翻译： 一种半导体器件，包括：具有掺杂半导体区域的衬底，栅极布线，下部导体结构，覆盖在下部结构上的绝缘层，并且具有延伸到下部导体结构的至少一个通孔，以及连接到上部导体结构 至少一个所述导体结构由至少一层金属，金属硅化物，金属氮化物，金属碳化物或导电氧化物膜形成，并且金属电镀 层设置在并附着在至少一层上。