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    Semiconductor device and manufacturing process thereof
    3.
    发明授权
    Semiconductor device and manufacturing process thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US06246105B1

    公开(公告)日：2001-06-12

    申请号：US09183594

    申请日：1998-10-30

    申请人： Yukio Morozumi ,  Takenori Asahi

    发明人： Yukio Morozumi ,  Takenori Asahi

    IPC分类号： H01L2358

    CPC分类号： H01L21/76864 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76877 ,  H01L23/53223 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device having an insulation protection film with increased reliability and improved device characteristics, and a manufacturing method thereof which improves the planarization and reduces the interlayer capacitance of the device. The semiconductor device has a semiconductor substrate including a MOS device, a plurality of wiring regions formed on the semiconductor substrate, and a protective insulation film formed on the top layer of the wiring regions. The protective insulation film includes a first silicon oxide film, a second silicon oxide film formed on the first silicon oxide film, and a silicon nitride film composing the top layer. The process of forming the protective insulation film includes the following steps: forming the first silicon oxide film through a reaction between a silicon compound and at least one of oxygen and a compound containing oxygen by chemical vapor deposition method, forming the second silicon oxide film on the first silicon oxide film by a condensation polymerization reaction between a silicon compound and hydrogen peroxide by chemical vapor deposition, conducting an annealing treatment at a temperature of 350-500° C., and forming the silicon nitride film.

    摘要翻译： 一种具有提高可靠性和改进的器件特性的绝缘保护膜的半导体器件及其制造方法，其改善了平面化并降低了器件的层间电容。 半导体器件具有包括MOS器件，形成在半导体衬底上的多个布线区域和形成在布线区域的顶层上的保护绝缘膜的半导体衬底。 保护绝缘膜包括第一氧化硅膜，形成在第一氧化硅膜上的第二氧化硅膜和构成顶层的氮化硅膜。 形成保护绝缘膜的过程包括以下步骤：通过化学气相沉积法通过硅化合物与氧和含氧化合物中的至少一种之间的反应形成第一氧化硅膜，形成第二氧化硅膜 通过化学气相沉积在硅化合物和过氧化氢之间进行缩聚反应的第一氧化硅膜，在350-500℃的温度下进行退火处理，并形成氮化硅膜。

    Semiconductor integrated circuit device having internal tensile and internal compression stress
    6.
    发明授权
    Semiconductor integrated circuit device having internal tensile and internal compression stress 失效
    具有内部拉伸和内部压缩应力的半导体集成电路器件

    公开(公告)号：US06569785B2

    公开(公告)日：2003-05-27

    申请号：US10177960

    申请日：2002-06-21

    申请人： Yukio Morozumi

    发明人： Yukio Morozumi

    IPC分类号： H01L2144

    CPC分类号： H01L21/76864 ,  H01L21/2855 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76828 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76882

    摘要： A semiconductor device has a structure that is capable of reducing warping of a semiconductor wafer when the semiconductor device is manufactured. The semiconductor device is manufactured by a method including the steps for forming an interlayer dielectric film having an internal compression stress and an interlayer dielectric film having an internal tensile stress. As a result, when semiconductor devices are manufactured, the tensile stress and the compression stress act on the semiconductor wafer. As a consequence, the overall stress that acts on the semiconductor wafer are reduced to a small level or to zero, and thus warping of the semiconductor wafer is reduced or eliminated when semiconductor devices are manufactured.

    摘要翻译： 半导体器件具有能够在制造半导体器件时减少半导体晶片翘曲的结构。 半导体器件通过包括用于形成具有内部压缩应力的层间电介质膜和具有内部拉伸应力的层间电介质膜的步骤的方法制造。 结果，当制造半导体器件时，拉伸应力和压缩应力作用在半导体晶片上。 结果，作用在半导体晶片上的总体应力被降低到小的水平或零，并且因此当制造半导体器件时，半导体晶片的翘曲被减小或消除。

    Method for manufacturing semiconductor device having interlayer dielectric film layers with like etch speeds
    7.
    发明授权
    Method for manufacturing semiconductor device having interlayer dielectric film layers with like etch speeds 失效
    具有类似蚀刻速度的层间绝缘膜层的半导体器件的制造方法

    公开(公告)号：US06358830B1

    公开(公告)日：2002-03-19

    申请号：US09470804

    申请日：1999-12-22

    申请人： Yukio Morozumi

    发明人： Yukio Morozumi

    IPC分类号： H01L2144

    CPC分类号： H01L21/76804 ,  H01L21/32051 ,  H01L21/76877

    摘要： An interlayer dielectric film is formed over a semiconductor substrate that may have a device element formed thereon. The interlayer dielectric film includes at least a first silicon oxide film and a second silicon oxide film as a cap layer being formed on the first silicon oxide film. The first silicon oxide film is formed by reacting SiH4 and H2O2 by a CVD method. The first silicon oxide film and the second silicon oxide film may be isotropically etched to form a through hole. The isotropic etching speed for the first silicon oxide film is the same as or generally the same as the etching speed for the second silicon oxide film (the cap layer). As a result, both the first silicon oxide film and the second silicon oxide film can be isotropically etched without causing excessive etching on the first silicon oxide film Therefore, the degree of freedom in isotropic etching is improved in isotropically etching multiple layers.

    摘要翻译： 在可以在其上形成有器件元件的半导体衬底上形成层间电介质膜。 层间电介质膜至少包括形成在第一氧化硅膜上的第一氧化硅膜和作为覆盖层的第二氧化硅膜。 通过CVD法使SiH 4和H 2 O 2反应形成第一氧化硅膜。 可以对第一氧化硅膜和第二氧化硅膜进行各向同性蚀刻以形成通孔。 第一氧化硅膜的各向同性蚀刻速度与第二氧化硅膜（盖层）的蚀刻速度相同或大致相同。 结果，可以对第一氧化硅膜和第二氧化硅膜进行各向同性蚀刻，而不会对第一氧化硅膜造成过度的蚀刻。因此，各向同性蚀刻的自由度在各向同性地蚀刻多层时得到改善。

    Microelectronic interlayer dielectric structure and methods of manufacturing same
    8.
    发明授权
    Microelectronic interlayer dielectric structure and methods of manufacturing same 失效
    微电子层间介质结构及其制造方法

    公开(公告)号：US5266525A

    公开(公告)日：1993-11-30

    申请号：US741285

    申请日：1991-08-07

    申请人： Yukio Morozumi

    发明人： Yukio Morozumi

    IPC分类号： H01L21/3205 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/522 ,  H01L21/441

    CPC分类号： H01L21/31055 ,  H01L21/76819 ,  Y10T428/24917 ,  Y10T428/24926

    摘要： A method of manufacturing an interlayer dielectric for microelectronic devices having multiple conducting layers provides a planarized surface for deposition of subsequent layers and further prevents cracking of spin-on-glass by limiting spin-on-glass thickness to about 0.4 .mu.m or less. A first dielectric layer is formed over a first conducting layer by means of reacting Si(OC.sub.2 H.sub.5).sub.4 and O.sub.2 at approximately 9 torr between 370.degree. C. to 400.degree. C., and a second dielectric layer is formed over the first dielectric layer by a method different than that used to form the first dielectric layer. After etching back the second dielectric layer, a spin-on-glass layer is formed. Spin-on-glass layer is etched back to provide a planar surface and a third dielectric layer is formed over the spin-on-glass layer. The resulting surface is ready for contact hole formation, deposition and patterning of subsequent conductive and insulating layers.

    摘要翻译： 制造具有多个导电层的微电子器件的层间电介质的方法提供了用于沉积后续层的平坦化表面，并且通过将旋涂玻璃厚度限制在约0.4μm或更小而进一步防止旋涂玻璃的开裂。 通过使Si（OC 2 H 5）4和O 2在大约9托下在370℃至400℃之间使第一导电层形成第一介电层，并且通过在第一介电层上形成第二介电层 与用于形成第一介电层的方法不同的方法。 在蚀刻回第二介电层之后，形成旋涂玻璃层。 旋转玻璃层被回蚀以提供平面表面，并且在旋涂玻璃层上形成第三介电层。 所得到的表面准备好接触孔形成，沉积和后续导电和绝缘层的图案化。

    Integrated semiconductor structure with incorporated alignment markings
    9.
    发明授权
    Integrated semiconductor structure with incorporated alignment markings 失效
    集成半导体结构，并入对准标记

    公开(公告)号：US5051807A

    公开(公告)日：1991-09-24

    申请号：US642121

    申请日：1991-01-14

    申请人： Yukio Morozumi

    发明人： Yukio Morozumi

    IPC分类号： H01L21/301 ,  H01L21/02 ,  H01L21/027 ,  H01L21/30 ,  H01L21/66 ,  H01L21/68 ,  H01L23/544

    CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/09701

    摘要： A semiconductor integrated circuit structure formed on a substrate and composed of a plurality of groups of integrated circuit chips each in the form of an elongated strip having a short dimension and a long dimension which is markedly longer than the short dimension, with adjacent chips in each group being spaced from one another by linear regions including a plurality of first linear regions extending parallel to the long dimension of the chips and at least one second linear region extending parallel to the short dimension of the chips, wherein, in each group, the at least one second linear region has a width greater than at least one of the first linear regions.

    摘要翻译： 一种半导体集成电路结构，其形成在基板上并且由多组集成电路芯片组成，每组集成电路芯片具有短尺寸和长尺寸的细长条形状，其长度明显长于短尺寸，每个相邻芯片 组彼此间隔开包括平行于芯片的长度尺寸延伸的多个第一线性区域和平行于芯片的短尺寸延伸的至少一个第二线性区域的线性区域，其中在每组中， 至少一个第二线性区域的宽度大于第一线性区域中的至少一个。

    Variable capacitor
    10.
    发明授权
    Variable capacitor 失效
    可变电容器

    公开(公告)号：US4068285A

    公开(公告)日：1978-01-10

    申请号：US683456

    申请日：1976-05-05

    申请人： Kuniharu Yamada ,  Yukio Morozumi ,  Keiichi Iuchi

    发明人： Kuniharu Yamada ,  Yukio Morozumi ,  Keiichi Iuchi

    IPC分类号： G04F5/06 ,  H01G5/013 ,  H01G5/06

    CPC分类号： H01G5/0136 ,  G04F5/066

    摘要： A variable capacitor is provided wherein a reinforcing plate is utilized in the rotor assembly in order to increase the range of the capacitor. The capacitor includes the stator plate and first electrode, the stator plate supporting a lead pin and a rotor positioning member, the rotor positioning member being rotatably mounted thereon. The rotor positioning member rotatably supports a uniformly thick rotor assembly in rotatable friction contact with the stator plate and first electrode. The rotor assembly includes a dielectric, a second capacitor electrode and a reinforcing plate, the thickenss of the dielectric determining the minimum value of capacitance of the variable capacitor. The rotor assembly also includes a fixed spring secured to the positioning member, the lead pin and fixed spring being adapted to facilitate use of variable capacitor in small-size electronic instrumentation.

    摘要翻译： 提供了一种可变电容器，其中在转子组件中使用加强板以增加电容器的范围。 电容器包括定子板和第一电极，定子板支撑引脚和转子定位构件，转子定位构件可转动地安装在其上。 转子定位构件可旋转地支撑均匀厚的转子组件，其与定子板和第一电极可旋转地摩擦接触。 转子组件包括电介质，第二电容器电极和加强板，电介质的厚度确定可变电容器的电容的最小值。 转子组件还包括固定到定位构件的固定弹簧，引导销和固定弹簧适于在小尺寸电子仪器中使用可变电容器。