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    Stencil/screen print apparatus
    1.
    发明申请
    Stencil/screen print apparatus 审中-公开
    模板/丝网印刷设备

    公开(公告)号：US20040107902A1

    公开(公告)日：2004-06-10

    申请号：US10643567

    申请日：2003-08-19

    Applicant: Micron Technology, Inc.

    Inventor： Tongbi Jiang ,  Chad A. Cobbley ,  John VanNortwick

    IPC: B05C005/00 ,  B05C011/11

    CPC classification number: B41C1/14 ,  B41N1/242 ,  H01L2224/4826 ,  H05K3/1225 ,  Y10S438/945

    Abstract: A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a substrate, such as an adhesive to a semiconductor die of a semiconductor wafer during a lead-on-chip (LOC) packaging process. In one embodiment, the stencil includes a coating applied to at least one surface of a pattern of the stencil or screen to retard running of the printable material onto the surface. In another embodiment, the stencil or screen includes a second coating applied to at least one other surface of the pattern to promote spreading of the printable material onto the substrate.

    Abstract translation: 公开了一种用于改进模板/丝网印刷质量的方法和装置。 在片上（LOC）包装过程中，模板或屏幕有助于将可印刷材料施加到基底上，例如对半导体晶片的半导体管芯的粘合剂。 在一个实施例中，模板包括施加到模板或筛网的图案的至少一个表面上的涂层，以阻止可印刷材料在表面上的运行。 在另一个实施例中，模板或丝网包括施加到图案的至少一个其他表面的第二涂层，以促进可印刷材料在基底上的铺展。

    Apparatus for improving stencil/screen print quality
    4.
    发明申请
    Apparatus for improving stencil/screen print quality 失效
    提高模板/丝网印刷质量的设备

    公开(公告)号：US20040089171A1

    公开(公告)日：2004-05-13

    申请号：US10701140

    申请日：2003-11-04

    Applicant: Micron Technology, Inc.

    Inventor： Tongbi Jiang ,  Chad A. Cobbley ,  John VanNortwick

    IPC: B41C001/14

    CPC classification number: B41C1/14 ,  B41N1/242 ,  H01L2224/4826 ,  H05K3/1225 ,  Y10S438/945

    Abstract: A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a substrate, such as an adhesive to a semiconductor die of a semiconductor wafer during a lead-on-chip (LOC) packaging process. In one embodiment, the stencil includes a coating applied to at least one surface of a pattern of the stencil or screen to retard running of the printable material onto the surface. In another embodiment, the stencil or screen includes a second coating applied to at least one other surface of the pattern to promote spreading of the printable material onto the substrate.

    Abstract translation: 公开了一种用于改进模板/丝网印刷质量的方法和装置。 在片上（LOC）包装过程中，模板或屏幕有助于将可印刷材料施加到基底上，例如对半导体晶片的半导体管芯的粘合剂。 在一个实施例中，模板包括施加到模板或筛网的图案的至少一个表面上的涂层，以阻止可印刷材料运动到表面上。 在另一个实施例中，模板或丝网包括施加到图案的至少一个其他表面的第二涂层，以促进可印刷材料在基底上的铺展。

    Electrical interconnect using locally conductive adhesive
    5.
    发明申请
    Electrical interconnect using locally conductive adhesive 有权
    使用局部导电胶的电气互连

    公开(公告)号：US20030203668A1

    公开(公告)日：2003-10-30

    申请号：US10132835

    申请日：2002-04-25

    Applicant: Micron Technology, Inc.

    Inventor： Chad A. Cobbley ,  Steve W. Heppler

    IPC: H01R004/38

    CPC classification number: H05K3/323 ,  C08K7/16 ,  C08K9/00 ,  C09J5/00 ,  C09J9/02 ,  C09J11/08 ,  C09J2205/11 ,  H01R4/04 ,  H05K3/321 ,  H05K2201/0224 ,  H05K2203/0278 ,  H05K2203/1163 ,  Y10T428/25 ,  Y10T428/263 ,  Y10T428/2982 ,  Y10T428/2989 ,  Y10T428/2991 ,  Y10T428/2998

    Abstract: An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at least one electrically nonconductive material is compressed between a first contact and a second contact. Compression to two contacts breaks the breakable coating exposing an electrically conducting material which makes contact with the first and second contacts. The electrically conducting material may be a metal conductor or a two-part reactive conductive resin/catalyst system. Also disclosed are processes for making such electrical interconnects and adhesives for use in making electrical interconnect.

    Abstract translation: 公开了一种各向异性导电互连件，其中包含具有至少一种非导电材料的可破坏涂层的颗粒的粘合剂在第一接触和第二接触之间被压缩。 对两个触点的压缩使可破坏的涂层暴露出与第一和第二触点接触的导电材料。 导电材料可以是金属导体或两部分反应性导电树脂/催化剂体系。 还公开了用于制造用于制造电互连的这种电互连和粘合剂的方法。

    Ball grid array packages with thermally conductive containers
    6.
    发明申请
    Ball grid array packages with thermally conductive containers 有权
    带导热容器的球栅阵列封装

    公开(公告)号：US20020187590A1

    公开(公告)日：2002-12-12

    申请号：US10209753

    申请日：2002-07-31

    Applicant: Micron Technology, Inc.

    Inventor： Todd O. Bolken ,  Chad A. Cobbley

    IPC: H01L023/34 ,  H01L021/56 ,  H01L023/40

    CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/561 ,  H01L23/367 ,  H01L23/4334 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  Y10S206/832 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: Ball grid array packages for semiconductor die include a thermally conductive container and a substrate that substantially enclose a semiconductor die. The die is positioned with respect to the container by thermally conductive supports formed in the container or attached to the container. The die contacts the supports so that the die and the container form a cavity that is at least partially filled with a thermally conductive material such as a conductive epoxy to promote thermal conduction between the die and the container. The die electrically connects to the substrate with bond wires that extend through an aperture in the substrate and attach to bond pads provided on the substrate. The aperture is typically filled with a protective layer of resin, epoxy, or other material that also encapsulates the bond wires. Solder balls are provided for electrical connection or the substrate and the die to a circuit board or other circuit element, and an encapsulant layer covers the surface of the substrate but permits electrical connection to the bond pads. Methods for packaging semiconductor die in such packages are also provided.

    Abstract translation: 用于半导体管芯的球栅阵列封装包括基本上封装半导体管芯的导热容器和衬底。 模具通过形成在容器中或附接到容器的导热支撑件相对于容器定位。 模具接触支撑件，使得模具和容器形成至少部分地填充有诸如导电环氧树脂的导热材料的空腔，以促进模具和容器之间的热传导。 模具通过键合线电连接到衬底，接合线延伸穿过衬底中的孔并且附接到设置在衬底上的接合焊盘。 孔通常填充有树脂，环氧树脂或也封装接合线的其它材料的保护层。 提供用于电连接的焊球或基板和管芯到电路板或其它电路元件，并且密封剂层覆盖基板的表面，但允许电连接到接合焊盘。 还提供了用于将这种封装中的半导体管芯封装的方法。

    Methods and apparatus for a thin stacked ball-grid array package
    7.
    发明申请
    Methods and apparatus for a thin stacked ball-grid array package 有权
    薄堆叠球栅阵列封装的方法和装置

    公开(公告)号：US20040084771A1

    公开(公告)日：2004-05-06

    申请号：US10288180

    申请日：2002-11-05

    Applicant: Micron Technology, Inc.

    Inventor： Todd O. Bolken ,  Chad A. Cobbley

    IPC: H01L023/52

    CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01012 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: A thin-stacked ball grid array (BGA) package is created by coupling a semi-conducting die to each of the opposing faces of an interposer having bond pads and circuitry on both faces. Solder balls on either side of each die and/or the interposer provide interconnects for stacking packages and also provide interconnects for module mounting. Each die may be electrically coupled to the interposer using wire bonds, nullflip-chipnull techniques, or other techniques as appropriate. A redistribution layer may also be formed on the outer surface of a bumped die to create connections between the die circuitry, ball pads and/or wire bonding pads. Because the two die are coupled to each other on opposite faces of the interposer, each package is extremely space-efficient. Individual packages may be stacked together prior to encapsulation or molding to further improve the stability and manufacturability of the stacked package.

    Abstract translation: 通过将半导体管芯耦合到具有在两个表面上的接合焊盘和电路的插入件的每个相对面而产生薄堆叠球栅阵列（BGA）封装。 每个管芯和/或插入件两侧的焊球提供用于堆叠封装的互连，并且还提供用于模块安装的互连。 可以使用引线键合“倒装芯片”技术或适当的其它技术将每个管芯电耦合到插入器。 还可以在凸起的裸片的外表面上形成再分配层，以在管芯电路，焊盘和/或引线接合焊盘之间形成连接。 因为两个管芯在插入件的相对面上彼此耦合，所以每个封装都非常节省空间。 单个包装可以在封装或模制之前堆叠在一起，以进一步提高堆叠包装的稳定性和可制造性。

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