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    Measuring apparatus that includes a chip having a through silicon via, a heater, and a stress sensor
    1.
    发明授权
    Measuring apparatus that includes a chip having a through silicon via, a heater, and a stress sensor 有权
    包括具有硅通孔，加热器和应力传感器的芯片的测量装置

    公开(公告)号：US08502224B2

    公开(公告)日：2013-08-06

    申请号：US12962658

    申请日：2010-12-08

    申请人： Ra-Min Tain ,  John H. Lau ,  Ming-Che Hsieh ,  Wei Li ,  Ming-Ji Dai

    发明人： Ra-Min Tain ,  John H. Lau ,  Ming-Che Hsieh ,  Wei Li ,  Ming-Ji Dai

    IPC分类号： H01L23/58

    CPC分类号： G01B7/18 ,  G01L1/18 ,  G01L1/2206 ,  H01L2224/16145

    摘要： A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface.

    摘要翻译： 提供了包括第一芯片，第一电路层，第一加热器，第一应力传感器和第二电路层的测量装置。 第一芯片具有第一通孔硅通孔，第一表面和与第一表面相对的第二表面。 第一电路层设置在第一表面上。 第一加热器和第一应力传感器设置在第一表面上并连接到第一电路层。 第二电路层设置在第二表面上。

    Fabricating method and testing method of semiconductor device and mechanical integrity testing apparatus
    2.
    发明授权
    Fabricating method and testing method of semiconductor device and mechanical integrity testing apparatus 有权
    半导体器件及机械完整性检测仪器的制作方法及测试方法

    公开(公告)号：US08397584B2

    公开(公告)日：2013-03-19

    申请号：US13023545

    申请日：2011-02-09

    申请人： Ming-Che Hsieh ,  John H. Lau ,  Ra-Min Tain

    发明人： Ming-Che Hsieh ,  John H. Lau ,  Ra-Min Tain

    IPC分类号： G01N3/00 ,  G01N3/20

    CPC分类号： H01L22/12 ,  G01N19/04 ,  H01L2224/16

    摘要： A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.

    摘要翻译： 提供了半导体器件和机械完整性测试装置的制造方法和测试方法。 一种物体包括晶片，绝缘层和多个导电柱。 晶片的表面在芯片区域外部具有多个第一盲孔和芯片区域内的多个第二盲孔。 绝缘层位于导电柱和第一盲孔的壁之间以及导电柱和第二盲孔的壁之间。 执行机械完整性测试以测试绝缘层，导电柱和第一盲孔的壁之间的结合强度。 在机械完整性测试中，在第一盲孔中的导电柱被限定之后，芯片区域中的导电柱电连接到元件。

    FABRICATING METHOD AND TESTING METHOD OF SEMICONDUCTOR DEVICE AND MECHANICAL INTEGRITY TESTING APPARATUS
    5.
    发明申请
    FABRICATING METHOD AND TESTING METHOD OF SEMICONDUCTOR DEVICE AND MECHANICAL INTEGRITY TESTING APPARATUS 有权
    半导体器件的制造方法和测试方法和机械完整性测试装置

    公开(公告)号：US20120135547A1

    公开(公告)日：2012-05-31

    申请号：US13023545

    申请日：2011-02-09

    申请人： Ming-Che Hsieh ,  John H. Lau ,  Ra-Min Tain

    发明人： Ming-Che Hsieh ,  John H. Lau ,  Ra-Min Tain

    IPC分类号： H01L21/66 ,  G01N3/00 ,  G01N3/20

    CPC分类号： H01L22/12 ,  G01N19/04 ,  H01L2224/16

    摘要： A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.

    摘要翻译： 提供了半导体器件和机械完整性测试装置的制造方法和测试方法。 一种物体包括晶片，绝缘层和多个导电柱。 晶片的表面在芯片区域外部具有多个第一盲孔和芯片区域内的多个第二盲孔。 绝缘层位于导电柱和第一盲孔的壁之间以及导电柱和第二盲孔的壁之间。 执行机械完整性测试以测试绝缘层，导电柱和第一盲孔的壁之间的结合强度。 在机械完整性测试中，在第一盲孔中的导电柱合格之后，芯片区域中的导电柱电连接到元件。

    MEASURING APPARATUS
    6.
    发明申请
    MEASURING APPARATUS 有权
    测量装置

    公开(公告)号：US20110309357A1

    公开(公告)日：2011-12-22

    申请号：US12962658

    申请日：2010-12-08

    申请人： Ra-Min Tain ,  John H. Lau ,  Ming-Che Hsieh ,  Wei Li ,  Ming-Ji Dai

    发明人： Ra-Min Tain ,  John H. Lau ,  Ming-Che Hsieh ,  Wei Li ,  Ming-Ji Dai

    IPC分类号： H01L25/07

    CPC分类号： G01B7/18 ,  G01L1/18 ,  G01L1/2206 ,  H01L2224/16145

    摘要： A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface.

    摘要翻译： 提供了包括第一芯片，第一电路层，第一加热器，第一应力传感器和第二电路层的测量装置。 第一芯片具有第一通孔硅通孔，第一表面和与第一表面相对的第二表面。 第一电路层设置在第一表面上。 第一加热器和第一应力传感器设置在第一表面上并连接到第一电路层。 第二电路层设置在第二表面上。

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08674491B2

    公开(公告)日：2014-03-18

    申请号：US13103107

    申请日：2011-05-09

    申请人： Chun-Kai Liu ,  John H. Lau ,  Ming-Ji Dai ,  Ra-Min Tain

    发明人： Chun-Kai Liu ,  John H. Lau ,  Ming-Ji Dai ,  Ra-Min Tain

    IPC分类号： H01L23/02

    CPC分类号： H01L23/38 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53276 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589

    摘要： A semiconductor device including a silicon substrate, a plurality of silicon nanowire clusters, a first circuit layer and a second circuit layer. The silicon substrate has a first surface, a second surface opposite to the first surface and a plurality of through holes. The silicon nanowire clusters are disposed in the through holes of the silicon substrate, respectively. The first circuit layer is disposed on the first surface and connected to the silicon nanowire clusters. The second circuit layer is disposed on the second surface and connected to the silicon nanowire clusters.

    摘要翻译： 一种半导体器件，包括硅衬底，多个硅纳米线簇，第一电路层和第二电路层。 硅衬底具有第一表面，与第一表面相对的第二表面和多个通孔。 硅纳米线簇分别设置在硅衬底的通孔中。 第一电路层设置在第一表面上并连接到硅纳米线簇。 第二电路层设置在第二表面上并连接到硅纳米线簇。

    TEST STRUCTURE AND MEASUREMENT METHOD THEREOF
    10.
    发明申请
    TEST STRUCTURE AND MEASUREMENT METHOD THEREOF 审中-公开
    测试结构及其测量方法

    公开(公告)号：US20120249176A1

    公开(公告)日：2012-10-04

    申请号：US13169051

    申请日：2011-06-27

    申请人： Heng-Chieh Chien ,  Ra-Min Tain ,  John H. Lau ,  Yu-Lin Chao ,  Ming-Ji Dai

    发明人： Heng-Chieh Chien ,  Ra-Min Tain ,  John H. Lau ,  Yu-Lin Chao ,  Ming-Ji Dai

    IPC分类号： G01R31/00

    CPC分类号： G01N25/18

    摘要： A test structure including a substrate, at least one conductive plug, a first conductive trace and a second conductive trace is provided. The substrate has a first area and a second area. The at lest one conductive plug is disposed in the substrate in the first area, wherein the conductive plug does not penetrate through the substrate.The first conductive trace is disposed on the conductive plug and on the substrate in the first area. The second conductive trace is disposed on the substrate in the second area. It is noted that the first conductive trace and the second conductive trace have the same material and the same shape. A measurement method of the above-mentioned test structure is also provided.

    摘要翻译： 提供了包括基板，至少一个导电插塞，第一导电迹线和第二导电迹线的测试结构。 衬底具有第一区域和第二区域。 至少一个导电插头设置在第一区域中的基板中，其中导电插塞不穿透基板。 第一导电迹线设置在第一区域中的导电插塞和基板上。 第二导电迹线设置在第二区域中的基板上。 注意，第一导电迹线和第二导电迹线具有相同的材料和相同的形状。 还提供了上述测试结构的测量方法。