摘要:
Provided are a semiconductor package with a reduced lead pitch, and a display panel assembly having the semiconductor package. The semiconductor package includes a film having a hole formed therein, a plating pattern formed under the film and forming a wire; a semiconductor chip placed in the hole and electrically connected to the plating pattern; and a first passivation layer formed at a side opposite to the semiconductor chip about the plating pattern and protecting the plating pattern.
摘要:
A test pad structure may include a plurality of test pads and a plurality of connection leads. A plurality of the test pads may be sequentially arranged from a wiring pattern on a substrate and arranged in rows parallel with one another. The plurality of the test pads may include a first group of test pads having at least one pad arranged in a first row and a second group of test pads having at least two pads. A plurality of the connection leads may extend from end portions of the wiring pattern to be connected to the plurality of test pads. A plurality of the connection leads may include at least one inner lead passing between the at least two pads of the second group of the test pads arranged in a second row closest to the first group of the test pads. The at least one inner lead may be connected to at least one pad of the at least two pads of the second group of the test pads arranged in a third row next to the second row.
摘要:
A test pad structure may include a plurality of test pads and a plurality of connection leads. A plurality of the test pads may be sequentially arranged from a wiring pattern on a substrate and arranged in rows parallel with one another. The plurality of the test pads may include a first group of test pads having at least one pad arranged in a first row and a second group of test pads having at least two pads. A plurality of the connection leads may extend from end portions of the wiring pattern to be connected to the plurality of test pads. A plurality of the connection leads may include at least one inner lead passing between the at least two pads of the second group of the test pads arranged in a second row closest to the first group of the test pads. The at least one inner lead may be connected to at least one pad of the at least two pads of the second group of the test pads arranged in a third row next to the second row.
摘要:
A solar cell module having a reduced thickness using a flip-chip approach includes a transparent substrate, a transparent electrode interconnection disposed on the transparent substrate, and a plurality of solar cells disposed on the transparent electrode interconnection, each solar cell having at least one protrusion formed on one surface of the solar cell, the protrusion being bonded to the transparent electrode interconnection.
摘要:
A semiconductor housing package may be provided. The semiconductor housing package may include a mold layer, a housing chip, a redistribution structure, and a housing node. The mold layer may surround and partially expose the housing chip. The redistribution structure may be electrically connected to the housing chip and may be disposed on the mold layer. The housing node may be in contact with the redistribution structures. The semiconductor housing package may be disposed on a semiconductor base package and may constitute a semiconductor package structure along with the semiconductor base package. The semiconductor package structure may be disposed on a processor-based system.
摘要:
A solar cell module includes a circuit board, a plurality of solar cells disposed on a first surface of the circuit board, a plurality of metal terminals formed on the first surface of the circuit board, and a plurality of wires electrically connecting the plurality of solar cells and the metal terminals. The circuit board has a second surface opposite to the first surface, the rear surface comprising openings corresponding to the metal terminals, the openings exposing the metal terminals to an exterior of the solar cell module, thus forming contact terminals for the solar cell module.
摘要:
A semiconductor housing package may be provided. The semiconductor housing package may include a mold layer, a housing chip, a redistribution structure, and a housing node. The mold layer may surround and partially expose the housing chip. The redistribution structure may be electrically connected to the housing chip and may be disposed on the mold layer. The housing node may be in contact with the redistribution structures. The semiconductor housing package may be disposed on a semiconductor base package and may constitute a semiconductor package structure along with the semiconductor base package. The semiconductor package structure may be disposed on a processor-based system.