公开(公告)号：US20050006749A1

公开(公告)日：2005-01-13

申请号：US10916445

申请日：2004-08-12

申请人： Nozomi Shimoishizaka ,  Ryuichi Sahara ,  Yoshifumi Nakamura ,  Takahiro Kumakawa ,  Shinji Murakami ,  Yutaka Harada

发明人： Nozomi Shimoishizaka ,  Ryuichi Sahara ,  Yoshifumi Nakamura ,  Takahiro Kumakawa ,  Shinji Murakami ,  Yutaka Harada

IPC分类号： H01L23/12 ,  H01L23/31 ,  H01L23/485 ,  H01L21/4763 ,  H01L23/02 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/3114 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05571 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

摘要： A low elasticity layer (20) having an opening in an electrode arranging area where element electrodes are disposed is provided on a main surface of a semiconductor substrate (10). On the low elasticity layer (20), lands (32) serving as external electrodes are disposed, and pads (30) on the element electrodes, the lands (32) and metal wires (31) for connecting them are integrally formed as a metal wiring pattern (33). A solder resist film (50) having an opening for exposing a part of each land (32) is formed, and a metal ball (40) is provided on the land (32) in the opening. The low elasticity layer (20) absorbs thermal stress and the like caused in heating or cooling the semiconductor device, so as to prevent disconnection of the metal wires (31).

摘要翻译： 在半导体衬底（10）的主表面上设置有在电极配置区域中设置有元件电极的开口的低弹性层（20）。 在低弹性层（20）上设置用作外部电极的焊盘（32），并且元件电极上的焊盘（30），用于连接的焊盘（32）和金属丝（31）一体地形成为金属 接线图案（33）。 形成具有用于暴露每个焊盘（32）的一部分的开口的阻焊膜（50），并且金属球（40）设置在开口中的焊盘（32）上。 低弹性层（20）吸收在加热或冷却半导体器件时引起的热应力等，以防止金属线（31）的断开。

公开(公告)号：US06812573B2

公开(公告)日：2004-11-02

申请号：US09886971

申请日：2001-06-25

申请人： Nozomi Shimoishizaka ,  Ryuichi Sahara ,  Yoshifumi Nakamura ,  Takahiro Kumakawa ,  Shinji Murakami ,  Yutaka Harada

发明人： Nozomi Shimoishizaka ,  Ryuichi Sahara ,  Yoshifumi Nakamura ,  Takahiro Kumakawa ,  Shinji Murakami ,  Yutaka Harada

IPC分类号： H01L2348

CPC分类号： H01L23/3114 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05571 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

摘要： A low elasticity layer (20) having an opening in an electrode arranging area where element electrodes are disposed is provided on a main surface of a semiconductor substrate (10). On the low elasticity layer (20), lands (32) serving as external electrodes are disposed, and pads (30) on the element electrodes, the lands (32) and metal wires (31) for connecting them are integrally formed as a metal wiring pattern (33). A solder resist film (50) having an opening for exposing a part of each land (32) is formed, and a metal ball (40) is provided on the land (32) in the opening. The low elasticity layer (20) absorbs thermal stress and the like caused in heating or cooling the semiconductor device, so as to prevent disconnection of the metal wires (31).

摘要翻译： 在半导体衬底（10）的主表面上设置有在电极配置区域中设置有元件电极的开口的低弹性层（20）。 在低弹性层（20）上设置用作外部电极的焊盘（32），并且元件电极上的焊盘（30），用于连接的焊盘（32）和金属丝（31）一体地形成为金属 布线图案（33）。 形成具有用于暴露每个焊盘（32）的一部分的开口的阻焊膜（50），并且金属球（40）设置在开口中的焊盘（32）上。 低弹性层（20）吸收在加热或冷却半导体器件时引起的热应力等，以防止金属线（31）的断开。

公开(公告)号：US06313532B1

公开(公告)日：2001-11-06

申请号：US09381381

申请日：1999-09-20

申请人： Nozomi Shimoishizaka ,  Ryuichi Sahara ,  Yoshifumi Nakamura ,  Takahiro Kumakawa ,  Shinji Murakami ,  Yutaka Harada

发明人： Nozomi Shimoishizaka ,  Ryuichi Sahara ,  Yoshifumi Nakamura ,  Takahiro Kumakawa ,  Shinji Murakami ,  Yutaka Harada

IPC分类号： H01L2348

CPC分类号： H01L23/3114 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05571 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

摘要： A low elasticity layer (20) having an opening in an electrode arranging area where element electrodes are disposed is provided on a main surface of a semiconductor substrate (10). On the low elasticity layer (20), lands (32) serving as external electrodes are disposed, and pads (30) on the element electrodes, the lands (32) and metal wires (31) for connecting them are integrally formed as a metal wiring pattern (33). A solder resist film (50) having an opening for exposing a part of each land (32) is formed, and a metal ball (40) is provided on the land (32) in the opening. The low elasticity layer (20) absorbs thermal stress and the like caused in heating or cooling the semiconductor device, so as to prevent disconnection of the metal wires (31).

摘要翻译： 在半导体衬底（10）的主表面上设置有在电极配置区域中设置有元件电极的开口的低弹性层（20）。 在低弹性层（20）上设置用作外部电极的焊盘（32），并且元件电极上的焊盘（30），用于连接的焊盘（32）和金属丝（31）一体地形成为金属 布线图案（33）。 形成具有用于暴露每个焊盘（32）的一部分的开口的阻焊膜（50），并且金属球（40）设置在开口中的焊盘（32）上。 低弹性层（20）吸收在加热或冷却半导体器件时引起的热应力等，以防止金属线（31）的断开。

公开(公告)号：US06924173B2

公开(公告)日：2005-08-02

申请号：US10387457

申请日：2003-03-14

申请人： Kazumi Watase ,  Hiroaki Fujimoto ,  Ryuichi Sahara ,  Nozomi Shimoishizaka ,  Takahiro Kumakawa ,  Kazuyuki Kaino ,  Yoshifumi Nakamura

发明人： Kazumi Watase ,  Hiroaki Fujimoto ,  Ryuichi Sahara ,  Nozomi Shimoishizaka ,  Takahiro Kumakawa ,  Kazuyuki Kaino ,  Yoshifumi Nakamura

IPC分类号： H01L25/18 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L25/07 ,  H01L21/58

CPC分类号： H01L24/97 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49872 ,  H01L24/45 ,  H01L24/48 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/85399 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207

摘要： Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.

摘要翻译： 公开了一种半导体器件10，其包括具有第一元件电极12的布置的第一半导体元件11，具有第二元件电极14的布置的第二半导体元件13，连接构件15，其将第一元件 电极12和第二元件电极14，覆盖第一半导体元件11的主表面11a和第二半导体元件13的背面13b的绝缘层17，形成在绝缘层17上的布线层22， 连接到暴露在开口部分21中的第一元件电极部分12b和形成为绝缘层17上的布线层22的一部分的外部电极23。

公开(公告)号：US06559528B2

公开(公告)日：2003-05-06

申请号：US09785503

申请日：2001-02-20

申请人： Kazumi Watase ,  Hiroaki Fujimoto ,  Ryuichi Sahara ,  Nozomi Shimoishizaka ,  Takahiro Kumakawa ,  Kazuyuki Kaino ,  Yoshifumi Nakamura

发明人： Kazumi Watase ,  Hiroaki Fujimoto ,  Ryuichi Sahara ,  Nozomi Shimoishizaka ,  Takahiro Kumakawa ,  Kazuyuki Kaino ,  Yoshifumi Nakamura

IPC分类号： H01L23498

CPC分类号： H01L24/97 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49872 ,  H01L24/45 ,  H01L24/48 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/85399 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207

摘要： Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.

摘要翻译： 公开了一种半导体器件10，其包括具有第一元件电极12的布置的第一半导体元件11，具有第二元件电极14的布置的第二半导体元件13，将第一元件电极的部分12b电连接在一起的连接构件15 12和第二元件电极14，覆盖第一半导体元件11的主表面11a和第二半导体元件13的背面13b的绝缘层17，形成在绝缘层17上并电连接到第二半导体元件13的布线层22的布线层22。 露出在开口部分21中的第一元件电极部分12b和作为布线层22的一部分形成在绝缘层17上的外部电极23。

公开(公告)号：US06512298B2

公开(公告)日：2003-01-28

申请号：US09984191

申请日：2001-10-29

申请人： Ryuichi Sahara ,  Kazumi Watase ,  Takahiro Kumakawa ,  Kazuyuki Kainoh ,  Nozomi Shimoishizaka

发明人： Ryuichi Sahara ,  Kazumi Watase ,  Takahiro Kumakawa ,  Kazuyuki Kainoh ,  Nozomi Shimoishizaka

IPC分类号： H01L2940

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L23/522 ,  H01L23/5227 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05552 ,  H01L2924/013

摘要： A first element electrode and a second element electrode connected electrically to a semiconductor element on a substrate are formed, and then an insulating film is formed on the substrate including the element electrodes. Thereafter, a first opening for exposing the first element electrode and a second opening for exposing the second element electrode are formed on the insulating film. Then, a first external electrode connected to the first element electrode via the first opening is formed immediately above the first element electrode. Furthermore, a second external electrode and a connecting wire having one end connected to the second element electrode via the second opening and the other end connected to the second external electrode are formed on the insulating film.

公开(公告)号：US06852616B2

公开(公告)日：2005-02-08

申请号：US10165279

申请日：2002-06-10

申请人： Ryuichi Sahara ,  Kazumi Watase ,  Takahiro Kumakawa ,  Kazuyuki Kainoh ,  Nozomi Shimoishizaka

发明人： Ryuichi Sahara ,  Kazumi Watase ,  Takahiro Kumakawa ,  Kazuyuki Kainoh ,  Nozomi Shimoishizaka

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L23/12 ,  H01L23/31 ,  H01L23/485 ,  H01L23/522 ,  H01L21/44

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L23/522 ,  H01L23/5227 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05552 ,  H01L2924/013

摘要： A first element electrode and a second element electrode connected electrically to a semiconductor element on a substrate are formed, and then an insulating film is formed on the substrate including the element electrodes. Thereafter, a first opening for exposing the first element electrode and a second opening for exposing the second element electrode are formed on the insulating film. Then, a first external electrode connected to the first element electrode via the first opening is formed immediately above the first element electrode. Furthermore, a second external electrode and a connecting wire having one end connected to the second element electrode via the second opening and the other end connected to the second external electrode are formed on the insulating film.

摘要翻译： 形成与基板上的半导体元件电连接的第一元件电极和第二元件电极，然后在包括元件电极的基板上形成绝缘膜。 此后，在绝缘膜上形成用于暴露第一元件电极的第一开口和用于暴露第二元件电极的第二开口。 然后，在第一元件电极的正上方形成有经由第一开口与第一元件电极连接的第一外部电极。 此外，在绝缘膜上形成第二外部电极和连接线，其一端经由第二开口连接到第二元件电极，而另一端连接到第二外部电极。

公开(公告)号：US07964475B2

公开(公告)日：2011-06-21

申请号：US11951441

申请日：2007-12-06

申请人： Yukiko Haraguchi ,  Takahiro Kumakawa ,  Takashi Yui ,  Kazumi Watase

发明人： Yukiko Haraguchi ,  Takahiro Kumakawa ,  Takashi Yui ,  Kazumi Watase

IPC分类号： H01L27/00 ,  H01L21/82

CPC分类号： H01L21/78

摘要： A modified layer 5 and an altered layer 8 are formed outside a dicing point of a dicing area 3. Thus without forming another interface between different physical properties on the dicing point, it is possible to prevent chipping from progressing along a crystal orientation from an interface between a semiconductor element 2 and a semiconductor substrate 1 and from a surface of the semiconductor element during dicing, thereby suppressing the development of chipping to the semiconductor element.

摘要翻译： 在切割区域3的切割点的外侧形成改质层5和改质层8.因此，在切割点的不同物理性质之间不形成另一界面，可以防止从界面 在半导体元件2和半导体基板1之间以及在切割期间从半导体元件的表面，从而抑制了对半导体元件的切屑的发展。

公开(公告)号：US07808059B2

公开(公告)日：2010-10-05

申请号：US11797292

申请日：2007-05-02

申请人： Takahiro Kumakawa

发明人： Takahiro Kumakawa

IPC分类号： H01L29/78

CPC分类号： B81C1/00873 ,  B23K26/40 ,  B23K26/53 ,  B23K2103/50 ,  H01L21/78

摘要： In a semiconductor substrate 1, a plurality of semiconductor elements 2 having diaphragm structures are formed in the form of cells in the longitudinal direction and the lateral direction, and V-grooves 3 are formed by anisotropic etching continuously on only division lines 4 parallel formed in one direction, out of the division lines 4 which are orthogonal to each other and divide the respective semiconductor elements 2 individually.

公开(公告)号：US20100015781A1

公开(公告)日：2010-01-21

申请号：US12570548

申请日：2009-09-30

申请人： Takahiro Kumakawa

发明人： Takahiro Kumakawa

IPC分类号： H01L21/304

CPC分类号： B81C1/00873 ,  B23K26/40 ,  B23K26/53 ,  B23K2103/50 ,  H01L21/78

摘要： In a semiconductor substrate 1, a plurality of semiconductor elements 2 having diaphragm structures are formed in the form of cells in the longitudinal direction and the lateral direction, and V-grooves 3 are formed by anisotropic etching continuously on only division lines 4 parallel formed in one direction, out of the division lines 4 which are orthogonal to each other and divide the respective semiconductor elements 2 individually.

摘要翻译： 在半导体基板1中，具有隔膜结构的多个半导体元件2以单元格的形式在长度方向和横向方向上形成，并且V形槽3通过各向异性蚀刻连续形成，仅在分开线4上平行形成 一个方向，分离线4彼此正交并分别分开各个半导体元件2。