公开(公告)号：US09184051B2

公开(公告)日：2015-11-10

申请号：US14346787

申请日：2012-09-21

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Peter Stauss ,  Philipp Drechsel

IPC: H01L21/02 ,  H01L33/00 ,  H01L33/12

CPC classification number: H01L21/0254 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/007 ,  H01L33/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of producing a nitride compound semiconductor component includes providing a growth substrate having a silicon surface, growing a buffer layer containing an aluminum-containing nitride compound semiconductor onto the silicon surface, growing a stress layer structure that produces a compressive stress, and growing a functional semiconductor layer sequence onto the stress layer structure, wherein the stress layer structure includes a first GaN semiconductor layer and a second GaN semiconductor layer, a masking layer is embedded in the first GaN semiconductor layer, an Al(Ga)N-intermediate layer that produces a compressive stress is disposed between the first GaN semiconductor layer and the second GaN semiconductor layer, and the stress layer structure does not contain further Al(Ga)N-intermediate layers.

Abstract translation: 制造氮化物半导体元件的方法包括：提供具有硅表面的生长衬底，将包含含铝氮化物半导体的缓冲层生长到所述硅表面上，生长产生压应力的应力层结构，以及生长 功能半导体层序列到应力层结构上，其中应力层结构包括第一GaN半导体层和第二GaN半导体层，掩模层嵌入第一GaN半导体层中，Al（Ga）N-中间层， 在第一GaN半导体层和第二GaN半导体层之间产生压应力，并且应力层结构不包含另外的Al（Ga）N中间层。

公开(公告)号：US20200243716A1

公开(公告)日：2020-07-30

申请号：US16067955

申请日：2017-02-22

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Werner Bergbauer ,  Thomas Lehnhardt ,  Jürgen Off ,  Lise Lahourcade ,  Philipp Drechsel

IPC: H01L33/12 ,  H01L33/00 ,  H01L33/24

Abstract: A method of producing a radiation-emitting semiconductor chip includes providing a growth substrate, epitaxially growing a buffer layer on the growth substrate such that a plurality of V-pits is generated in the buffer layer, epitaxially growing a radiation-generating active semiconductor layer sequence on the buffer layer, wherein the structure of the V-pits continues into the active semiconductor layer sequence, epitaxially growing a further layer sequence on the active semiconductor layer sequence, wherein the structure of the V-pits continues into the further layer sequence, selectively removing the further layer sequence from facets of the V-pits, wherein the further layer sequence remains on a main surface of the active semiconductor layer sequence, and epitaxially growing a p-doped semiconductor layer that completely or partially fills the V-pits.

公开(公告)号：US20200119228A1

公开(公告)日：2020-04-16

申请号：US16303571

申请日：2017-05-18

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Thomas Lehnhardt ,  Werner Bergbauer ,  Jürgen Off ,  Lise Lahourcade ,  Philipp Drechsel

IPC: H01L33/24 ,  H01L33/38 ,  H01L33/32 ,  H01L33/06 ,  H01L33/00 ,  H01L33/18

Abstract: A component having an enhanced efficiency and a method for producing a component are disclosed. In an embodiment, a component includes a semiconductor layer sequence comprising a p-conducting semiconductor layer, an n-conducting semiconductor layer and an active zone located therebetween, wherein the active zone comprises recesses on a side of the p-conducting semiconductor layer, each recess having facets extending obliquely to a main surface of the active zone, and wherein the p-conducting semiconductor layer extends into the recesses, and a barrier structure, wherein the active zone is arranged between the barrier structure and the n-conducting semiconductor layer so that an injection of positively charged charge carriers into the active zone via the main surface is hindered in a targeted manner so that an injection of positively charged charge carriers into the active zone via the facets is promoted.

公开(公告)号：US20170012165A1

公开(公告)日：2017-01-12

申请号：US15120552

申请日：2015-02-24

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Joachim Hertkorn ,  Werner Bergbauer ,  Philipp Drechsel

IPC: H01L33/00 ,  H01L33/20 ,  H01L33/58 ,  H01L33/12

CPC classification number: H01L33/007 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/20 ,  H01L33/58

Abstract: A method of producing a semiconductor layer sequence includes providing a growth substrate having a growth surface on a growth side, growing a first nitride semiconductor layer on the growth side, growing a second nitride semiconductor layer on the first nitride semiconductor layer, wherein the second nitride semiconductor layer includes at least one opening or at least one opening is produced in the second nitride semiconductor layer or at least one opening is created in the second nitride semiconductor layer during the growing process, removing at least one part of the first nitride semiconductor layer through the openings in the second nitride semiconductor layer, and growing a third nitride semiconductor layer on the second nitride semiconductor layer, wherein the third nitride semiconductor layer covers the openings at least in places.

Abstract translation: 一种制造半导体层序列的方法包括提供在生长侧具有生长表面的生长衬底，在生长侧生长第一氮化物半导体层，在第一氮化物半导体层上生长第二氮化物半导体层，其中第二氮化物 半导体层包括至少一个开口或在第二氮化物半导体层中产生至少一个开口，或者在生长过程中在第二氮化物半导体层中产生至少一个开口，通过第二氮化物半导体层的至少一部分去除第一氮化物半导体层的至少一部分 所述第二氮化物半导体层中的所述开口，以及在所述第二氮化物半导体层上生长第三氮化物半导体层，其中所述第三氮化物半导体层至少覆盖所述开口。

公开(公告)号：US20150228858A1

公开(公告)日：2015-08-13

申请号：US14427687

申请日：2013-09-25

Applicant: OSRAM OPTO SEMICONDUCTORS GMBH

Inventor： Werner Bergbauer ,  Philipp Drechsel ,  Peter Stauss ,  Patrick Rode

IPC: H01L33/32 ,  H01L33/02

CPC classification number: H01L33/325 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0254 ,  H01L33/007 ,  H01L33/025 ,  H01L33/12 ,  H01L33/32

Abstract: An optoelectronic component includes a layer structure which has a first gallium nitride layer and an aluminum-containing nitride intermediate layer. In this case, the aluminum-containing nitride intermediate layer adjoins the first gallium nitride layer. The layer structure has an undoped second gallium nitride layer which adjoins the aluminum-containing nitride intermediate layer.

Abstract translation: 光电子部件包括具有第一氮化镓层和含铝氮化物中间层的层结构。 在这种情况下，含铝氮化物中间层与第一氮化镓层相邻。 层结构具有与含铝氮化物中间层相邻的未掺杂的第二氮化镓层。

公开(公告)号：US10950752B2

公开(公告)日：2021-03-16

申请号：US16067955

申请日：2017-02-22

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Werner Bergbauer ,  Thomas Lehnhardt ,  Jürgen Off ,  Lise Lahourcade ,  Philipp Drechsel

IPC: H01L33/12 ,  H01L33/00 ,  H01L33/24

Abstract: A method of producing a radiation-emitting semiconductor chip includes providing a growth substrate, epitaxially growing a buffer layer on the growth substrate such that a plurality of V-pits is generated in the buffer layer, epitaxially growing a radiation-generating active semiconductor layer sequence on the buffer layer, wherein the structure of the V-pits continues into the active semiconductor layer sequence, epitaxially growing a further layer sequence on the active semiconductor layer sequence, wherein the structure of the V-pits continues into the further layer sequence, selectively removing the further layer sequence from facets of the V-pits, wherein the further layer sequence remains on a main surface of the active semiconductor layer sequence, and epitaxially growing a p-doped semiconductor layer that completely or partially fills the V-pits.

公开(公告)号：US20180062031A1

公开(公告)日：2018-03-01

申请号：US15557600

申请日：2016-03-29

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Asako Hirai ,  Tobias Meyer ,  Philipp Drechsel ,  Peter Stauß ,  Anna Nirschl ,  Alvaro Gomez-Iglesias ,  Tobias Niebling ,  Bastian Galler

IPC: H01L33/06 ,  H01L31/0352 ,  H01L29/15

CPC classification number: H01L31/0352 ,  H01L29/151 ,  H01L29/152 ,  H01L31/035236 ,  H01L33/06

Abstract: An optoelectronic semiconductor chip is disclosed. In an embodiment the chip includes an active zone with a multi-quantum-well structure, wherein the multi-quantum-well structure comprises multiple quantum-well layers and multiple barrier layers, which are arranged sequentially in an alternating manner along a growth direction, wherein the multi-quantum-well structure has at least one emission region and multiple transport regions which are arranged sequentially in an alternating manner in a direction perpendicular to the growth direction, wherein at least one of the quantum-well layers and the barrier layers are thinner in the transport regions than in the emission regions, and wherein the quantum-well layers in the transport regions and in the emission regions are oriented perpendicularly to the growth direction with exception of a junction region between adjacent transport regions and emission regions.

公开(公告)号：US09660137B2

公开(公告)日：2017-05-23

申请号：US14891924

申请日：2014-05-28

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Werner Bergbauer ,  Philipp Drechsel ,  Peter Stauss ,  Patrick Rode

IPC: H01L33/00 ,  H01L21/02 ,  H01L33/12 ,  H01L33/06 ,  H01L33/02

CPC classification number: H01L33/0075 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/0254 ,  H01L33/0066 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/025 ,  H01L33/06 ,  H01L33/12

Abstract: A method is provided for producing a nitride compound semiconductor device. A growth substrate has a silicon surface. A buffer layer, which comprises AlxInyGa1-x-yN with 0≦x≦1, 0≦y≦1 and x+y≦1, is grown onto the silicon surface of the substrate. A semiconductor layer sequence is grown onto the buffer layer. The buffer layer includes a material composition that varies in such a way that a lateral lattice constant of the buffer layer increases stepwise or continuously in a first region and decreases stepwise or continuously in a second region, which follows the first region in the growth direction. At an interface with the semiconductor layer sequence, the buffer layer includes a smaller lateral lattice constant than a semiconductor layer of the semiconductor layer sequence adjoining the buffer layer.

公开(公告)号：US20190109246A1

公开(公告)日：2019-04-11

申请号：US16196915

申请日：2018-11-20

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Asako Hirai ,  Tobias Meyer ,  Philipp Drechsel ,  Peter Stauß ,  Anna Nirschl ,  Alvaro Gomez-Iglesias ,  Tobias Niebling ,  Bastian Galler

IPC: H01L31/0352 ,  H01L33/06 ,  H01L29/15

CPC classification number: H01L31/0352 ,  H01L29/151 ,  H01L29/152 ,  H01L31/035236 ,  H01L33/06

Abstract: An optoelectronic semiconductor chip is disclosed. In an embodiment a chip includes an active zone with a multi-quantum-well structure, wherein the multi-quantum-well structure includes multiple quantum-well layers and multiple barrier layers, which are arranged sequentially in an alternating manner along a growth direction and which each extend continuously over the entire multi-quantum-well structure, wherein seen in a cross-section parallel to the growth direction, the multi-quantum-well structure has at least one emission region and multiple transport regions, wherein the quantum-well layers and the barrier layers are thinner in the transport regions than in the emission region, wherein, along the growth direction, the transport regions have a constant width, and wherein the quantum-well layers and the barrier layers are oriented parallel to one another in the emission region and in the transport regions.

公开(公告)号：US10147601B2

公开(公告)日：2018-12-04

申请号：US15304488

申请日：2015-04-13

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Philipp Drechsel ,  Werner Bergbauer ,  Juergen Off ,  Peter Stauss

IPC: H01L31/0256 ,  H01L21/02 ,  H01L33/00 ,  H01L33/12 ,  H01L33/32

Abstract: What is specified is a method for producing a layer structure (10) as a buffer layer of a semiconductor component, said method comprising the following steps: a) provision of a carrier (1), which has a silicon surface (1a), b) deposition of a first layer sequence (2), which comprises a seeding layer (21) containing aluminum and nitrogen, on the silicon surface (1a) of the carrier (1) along a stacking direction (H) running perpendicular to a main plane of extent of the carrier (1), c) three-dimensional growth of a 3D-GaN layer (3), which is formed with gallium nitride, on a top surface (2a) of the first layer sequence (2) which is remote from the silicon surface (1a), d) two-dimensional growth of a 2D-GaN layer (4), which is formed with gallium nitride, on the outer surfaces (3a) of the 3D-GaN layer (3) which are remote from the silicon surface (1a).