公开(公告)号：US06812741B2

公开(公告)日：2004-11-02

申请号：US10394677

申请日：2003-03-21

申请人： Osamu Shibata ,  Yoshiyuki Saito ,  Yukihiro Fukumoto

发明人： Osamu Shibata ,  Yoshiyuki Saito ,  Yukihiro Fukumoto

IPC分类号： H03K190175

CPC分类号： H04L25/0292 ,  G06F13/4086 ,  H04L5/16 ,  H04L25/0278 ,  H04L25/028

摘要： A bidirectional transmission circuit for inputting/outputting a signal from/onto a bidirectional transmission line includes: a transceiver for transmitting/receiving a signal; a first element having an impedance; a second element being a short line; and a switching unit for coupling the transceiver to the bidirectional transmission line via the first element when the transceiver transmits a signal, and coupling the transceiver to the bidirectional transmission line via the second element when the transceiver receives a signal.

摘要翻译： 用于从双向传输线路输入/输出信号的双向传输电路包括：用于发送/接收信号的收发器; 具有阻抗的第一元件; 第二个元素是短线; 以及切换单元，用于当收发器发送信号时，经由第一元件将收发器耦合到双向传输线，并且当收发器接收到信号时，将收发器经由第二元件耦合到双向传输线。

公开(公告)号：US20090290274A1

公开(公告)日：2009-11-26

申请号：US12468475

申请日：2009-05-19

申请人： Hiroshi SUENAGA ,  Yoshiyuki Saito ,  Osamu Shibata ,  Yukihiro Fukumoto

发明人： Hiroshi SUENAGA ,  Yoshiyuki Saito ,  Osamu Shibata ,  Yukihiro Fukumoto

IPC分类号： H02H9/04 ,  H05K1/02

CPC分类号： G06K19/07743 ,  G06K19/07732 ,  G06K19/07735 ,  H01L2224/16225 ,  H05K1/0237 ,  H05K1/0259 ,  H05K1/112 ,  H05K1/117 ,  H05K2201/094 ,  H05K2201/09736 ,  H05K2201/09845 ,  H05K2201/10159 ,  H05K2201/10174 ,  H05K2201/10674

摘要： According to the present invention, the setting height position of a first terminal is set to be lower than the setting height position of a second terminal on the terminal formation surface of a printed substrate, so that the protection of an internal circuit and the transmission of a high-speed signal can be both achieved.

摘要翻译： 根据本发明，第一端子的设定高度位置被设定为低于印刷基板的端子形成面上的第二端子的设定高度位置，使得内部电路的保护和传输 可以实现高速信号。

公开(公告)号：US06901343B2

公开(公告)日：2005-05-31

申请号：US10029571

申请日：2001-12-20

申请人： Eiji Takahashi ,  Yukihiro Fukumoto ,  Yoshiyuki Saito ,  Osamu Shibata ,  Shinichi Tanimoto ,  Takeshi Nakayama

发明人： Eiji Takahashi ,  Yukihiro Fukumoto ,  Yoshiyuki Saito ,  Osamu Shibata ,  Shinichi Tanimoto ,  Takeshi Nakayama

IPC分类号： G06F17/50 ,  H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H04L9/32

CPC分类号： G06F17/5068 ,  H05K1/0275 ,  H05K1/0298 ,  H05K1/114 ,  H05K2201/09627 ,  H05K2201/09772 ,  H05K2201/10151

摘要： A signal line, being in a six-layer board and connecting terminal 102 of component 101 with terminal 115 of component 114, requires tamper-resistance. The signal line is composed of foil 103 on an outside layer, a via 104, foil 111 on the third layer, via 105, foil 112 on the fourth layer, via 106, and foil 113 on the sixth layer. Portions of the signal line that exist on outside layers are all hidden under circuit components. Foil 103 and an end of via 104 are placed under component 101 on first layer 116, an end of via 105 is placed under component 107 on layer 116, an end of via 106 is placed under component 108 on layer 116, the other end of via 104 is placed under component 109 on sixth layer 121, the other end of via 105 is placed under component 110 on layer 121, and foil 113 and the other end of via 106 are placed under component 114 on layer 121.

摘要翻译： 在组件101的六层板和连接端子102与元件114的端子115之间的信号线需要防篡改。 信号线由外层的箔103，通孔104，第三层上的箔111，通孔105，第四层上的箔112，第106层和第六层上的箔113组成。 存在于外层的信号线部分都隐藏在电路元件下面。 箔103和通孔104的末端放置在第一层116上的部件101下方，通孔105的端部放置在层116上的部件107的下方，通孔106的端部放置在层116上的部件108的下方，另一端 通孔104被放置在第六层121上的部件109的下方，通孔105的另一端被放置在层121上的部件110下方，并且箔113和通孔106的另一端放置在层121上的部件114下方。

公开(公告)号：US06629302B2

公开(公告)日：2003-09-30

申请号：US09746886

申请日：2000-12-22

申请人： Shinji Miura ,  Yukihiro Fukumoto ,  Hirokazu Uemura ,  Yoshiyuki Saito ,  Hiroshi Ikeda ,  Takeshi Nakayama ,  Osamu Shibata ,  Shinichi Tanimoto

发明人： Shinji Miura ,  Yukihiro Fukumoto ,  Hirokazu Uemura ,  Yoshiyuki Saito ,  Hiroshi Ikeda ,  Takeshi Nakayama ,  Osamu Shibata ,  Shinichi Tanimoto

IPC分类号： G06F945

CPC分类号： G06F17/5068

摘要： A design aiding apparatus and a method, and a storage medium storing a design aiding program enable the efficient layout design of components in a multilayer wiring board formed by laminating a plurality of wiring layers. The design aiding apparatus includes (a) a first acquiring unit for acquiring information showing a first location in a lamination direction of the wiring layers, (b) a second acquiring unit for acquiring information showing a second location on a two-dimensional plane that is orthogonal to the lamination direction, and (c) a placement unit for generating information showing a space to be occupied when the component is placed in such a manner that a placement reference point of the component coincides with the second location that is on the two-dimensional plane including the first location. According to the above construction, the present invention is capable of aiding layout design of components in the wiring board.

摘要翻译： 设计辅助装置和方法以及存储设计辅助程序的存储介质使得能够通过层叠多个布线层而形成的多层布线板中的部件的有效布局设计。 设计辅助装置包括：（a）第一获取单元，用于获取表示布线层的层叠方向上的第一位置的信息，（b）第二获取单元，用于获取表示二维平面上的第二位置的信息， 与所述层叠方向正交，以及（c）放置单元，用于产生表示当所述部件以所述部件的放置基准点与所述第二位置的所述第二位置一致的方式配置时要占据的空间的信息， 包括第一位置的三维平面。 根据上述结构，本发明能够帮助布线板中部件的布局设计。

公开(公告)号：US07843224B2

公开(公告)日：2010-11-30

申请号：US12262613

申请日：2008-10-31

申请人： Hiroshi Suenaga ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Masayuki Toyama ,  Kyoko Hirata

发明人： Hiroshi Suenaga ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Masayuki Toyama ,  Kyoko Hirata

IPC分类号： H03K19/094

CPC分类号： H04L25/028 ,  H04L25/0272

摘要： An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.

摘要翻译： 本发明的目的是实现在两个传输系统之间切换的接口电路中的输出级驱动器的面积的减小。 接口电路具有两个驱动电路和驱动控制电路，该电路可以在作为电压驱动系统和电流驱动系统的两个驱动系统之间切换。 两个驱动电路通过驱动控制电路连接到电源电位。 通过选择电路输入输入信号的两个输入信号和反相逻辑信号。 根据输入到驱动控制电路的控制信号，接口电路在电压驱动型单端传输系统和电流驱动型差动传输系统之间切换。

公开(公告)号：US20090108872A1

公开(公告)日：2009-04-30

申请号：US12262613

申请日：2008-10-31

申请人： Hiroshi Suenaga ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Masayuki Toyama ,  Kyoko Hirata

发明人： Hiroshi Suenaga ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Masayuki Toyama ,  Kyoko Hirata

IPC分类号： H03K19/0175

CPC分类号： H04L25/028 ,  H04L25/0272

摘要： An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.

摘要翻译： 本发明的目的是实现在两个传输系统之间切换的接口电路中的输出级驱动器的面积的减小。 接口电路具有两个驱动电路和驱动控制电路，该电路可以在作为电压驱动系统和电流驱动系统的两个驱动系统之间切换。 两个驱动电路通过驱动控制电路连接到电源电位。 通过选择电路输入输入信号的两个输入信号和反相逻辑信号。 根据输入到驱动控制电路的控制信号，接口电路在电压驱动型单端传输系统和电流驱动型差动传输系统之间切换。

公开(公告)号：US20060071320A1

公开(公告)日：2006-04-06

申请号：US11242955

申请日：2005-10-05

申请人： Osamu Shibata ,  Yoshiyuki Saito

发明人： Osamu Shibata ,  Yoshiyuki Saito

IPC分类号： H01L23/52

CPC分类号： H01L23/60 ,  H01L23/552 ,  H01L23/66 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/4911 ,  H01L2224/49113 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00

摘要： Fine-pitch first and second bonding pads are formed on a chip along its perimeter. The first bonding pads are formed at the peripheral parts on the chip, while the second bonding pads are formed inside the peripheral parts. An ESD protection circuit is connected to the first bonding pad, and an I/O circuit is connected to the second bonding pad. First and second bonding wires connect the first and second bonding pads to the same package pin, respectively. The second bonding wire is configured to be sufficiently longer than the first bonding wire, regardless of the pitch of the first bonding pads.

摘要翻译： 细间距第一和第二接合焊盘沿其周边形成在芯片上。 第一接合焊盘形成在芯片的周边部分，而第二接合焊盘形成在周边部分内部。 ESD保护电路连接到第一焊盘，并且I / O电路连接到第二接合焊盘。 第一和第二接合线分别将第一和第二接合焊盘连接到相同的封装引脚。 第二接合线被配置为比第一接合线充分长，而与第一接合焊盘的间距无关。

公开(公告)号：US20060050820A1

公开(公告)日：2006-03-09

申请号：US10539235

申请日：2004-02-10

申请人： Hirotsugu Kawada ,  Yoshiyuki Saito ,  Osamu Shibata ,  Hiroshi Suenaga ,  Takahisa Sakai ,  Toshitomo Umei ,  Takashi Akita ,  Yuji Mizuguchi ,  Noboru Katta

发明人： Hirotsugu Kawada ,  Yoshiyuki Saito ,  Osamu Shibata ,  Hiroshi Suenaga ,  Takahisa Sakai ,  Toshitomo Umei ,  Takashi Akita ,  Yuji Mizuguchi ,  Noboru Katta

IPC分类号： H04L7/00

CPC分类号： H04L7/00 ,  H04L7/0334

摘要： A signal receiver (11) receives an analog signal via a twisted pair cable (31). An A/D converter (12) converts the analog signal to a digital signal. A phase detection unit (14) detects the phase of the digital signal, and generates a reception timing signal. A transmission timing generation unit (15) controls, based on the reception timing signal, timing for a transmission processing unit (16) to output the digital signal such that the reception signal (point A) and a transmission signal (point D) are different in phase by a predetermined degree. The transmission processing unit (16) outputs, in accordance with the timing, a digital signal obtained by performing mapping on data inputted from a connection device (20). A D/A converter (17) converts the digital signal to an analog signal. A signal transmitter (18) transmits the analog signal via a twisted pair cable (32).

摘要翻译： 信号接收器（11）经由双绞线电缆（31）接收模拟信号。 A / D转换器（12）将模拟信号转换成数字信号。 相位检测单元（14）检测数字信号的相位，并产生接收定时信号。 发送定时生成单元（15）基于接收定时信号，控制发送处理单元（16）输出数字信号的定时，使得接收信号（点A）和发送信号（点D）不同 同时预定的程度。 发送处理单元（16）根据定时输出通过对从连接装置（20）输入的数据进行映射而获得的数字信号。 D / A转换器（17）将数字信号转换成模拟信号。 信号发送器（18）经由双绞线电缆（32）发送模拟信号。

公开(公告)号：US20050162184A1

公开(公告)日：2005-07-28

申请号：US11038436

申请日：2005-01-21

申请人： Osamu Shibata ,  Toru Iwata ,  Yoshiyuki Saito ,  Satoshi Takahashi ,  Wataru Itoh

发明人： Osamu Shibata ,  Toru Iwata ,  Yoshiyuki Saito ,  Satoshi Takahashi ,  Wataru Itoh

IPC分类号： H03K19/003 ,  H04L25/02

CPC分类号： H04L25/0278 ,  H04L25/0292

摘要： First and second transmission lines and are connected to each other in series. A first terminator is connected to the first transmission line in parallel, and is provided externally of a semiconductor device. A second terminator is connected to the second transmission line in parallel, and is provided inside the semiconductor device. The values of the first and second terminator are adjusted so that the combined resistance value of first and second terminator and the second transmission line matches with the impedance of the first transmission line. Impedance matching of the entire transmission line can be achieved with this simple construction, thus, a stable, high quality signal can be transmitted.

摘要翻译： 第一和第二传输线并且彼此串联连接。 第一终端器并联连接到第一传输线，并且设置在半导体器件的外部。 第二终端器并联连接到第二传输线，并且设置在半导体器件的内部。 调整第一和第二终端器的值，使得第一和第二终端器与第二传输线的组合电阻值与第一传输线的阻抗匹配。 可以通过这种简单的结构实现整个传输线的阻抗匹配，从而可以传输稳定的高质量信号。

公开(公告)号：US07886085B2

公开(公告)日：2011-02-08

申请号：US12295051

申请日：2007-02-20

申请人： Hiroshi Suenaga ,  Osamu Shibata ,  Noriaki Takeda ,  Toru Iwata ,  Takaharu Yoshida ,  Yoshiyuki Saito

发明人： Hiroshi Suenaga ,  Osamu Shibata ,  Noriaki Takeda ,  Toru Iwata ,  Takaharu Yoshida ,  Yoshiyuki Saito

IPC分类号： G06F13/00 ,  G06F3/00

CPC分类号： H04L7/10 ,  G06F1/12 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/044 ,  H04L7/046

摘要： An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time. A removable memory device that transmits/receives data to and from a host terminal, which includes: a clock reception section that receives a transmission/reception clock, which is used for transmitting/receiving data between the host terminal and the removable memory device, from the host terminal; a phase synchronization pattern generation section that generates a phase synchronization pattern, which is for adjusting a phase of internal reception clock which the host terminal incorporates for receiving data from the removable memory device, based on the transmission/reception clock; and a transmission section that transmits the generated phase synchronization pattern to the host terminal, and in which the phase synchronization pattern includes a first level signal which lasts for at least two cycles, and a second level signal which follows the first level signal and lasts for one cycle, is provided.

摘要翻译： 本发明的目的是提供一种提高数据传输效率的技术，其允许同时正确地接收数据。 一种向主机终端发送/接收数据的可移动存储装置，包括：接收用于在主机终端和可移动存储装置之间发送/接收数据的发送/接收时钟的时钟接收部分， 主机终端; 相位同步模式生成部，其基于所述发送接收时钟生成相位同步模式，所述相位同步模式用于调整所述主机终端结合的用于从所述可移动存储装置接收数据的内部接收时钟的相位; 以及发送部，其将所生成的相位同步模式发送到所述主机终端，并且所述相位同步模式包括持续至少两个周期的第一电平信号，以及在所述第一电平信号之后持续的第二电平信号， 提供一个循环。