公开(公告)号：US20120018901A1

公开(公告)日：2012-01-26

申请号：US12840937

申请日：2010-07-21

申请人： Patrick Variot ,  Qwai Low ,  Zafer Kutlu

发明人： Patrick Variot ,  Qwai Low ,  Zafer Kutlu

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L23/3675 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49816 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/014

摘要： A method of manufacturing a flip-chip package and a flip-chip package manufactured by such method. In one embodiment, the method includes: (1) mounting a die to a first die, (2) encapsulating the second die with a molding compound and (3) selectively ablating the molding compound based on an expected heat generation of portions of the second die to reduce a thickness of the molding compound proximate the portions.

摘要翻译： 一种通过这种方法制造倒装芯片封装和倒装芯片封装的方法。 在一个实施例中，该方法包括：（1）将模具安装到第一模具，（2）用模塑料封装第二模具，以及（3）基于第二模具部分的预期发热量选择性地烧蚀模塑料 模制以减小靠近该部分的模塑料的厚度。

公开(公告)号：US20080290502A1

公开(公告)日：2008-11-27

申请号：US11753591

申请日：2007-05-25

申请人： Zafer Kutlu

发明人： Zafer Kutlu

IPC分类号： H01L23/36 ,  H01L21/58 ,  H01L23/488

CPC分类号： H01L23/42 ,  H01L23/10 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1146 ,  H01L2224/1148 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/2746 ,  H01L2224/29 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/73153 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/83191 ,  H01L2224/83815 ,  H01L2224/9221 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

摘要： An integrated circuit die includes a circuit surface and a back surface opposite the circuit surface. An underbump metallurgy is formed on a back surface. A layer of solder is formed on the underbump metallurgy.

摘要翻译： 集成电路管芯包括电路表面和与电路表面相对的后表面。 后表面上形成下水道冶金。 在下水道冶金上形成一层焊料。

公开(公告)号：US07479703B1

公开(公告)日：2009-01-20

申请号：US11772267

申请日：2007-07-02

申请人： Zafer Kutlu

发明人： Zafer Kutlu

IPC分类号： H01L23/48

CPC分类号： H01L23/562 ,  H01L23/29 ,  H01L2223/54433 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

摘要： An integrated circuit package includes an integrated circuit die having a circuit surface and a back surface opposite the circuit surface. A layer of ductile material is deposited on the back surface of the integrated circuit die.

摘要翻译： 集成电路封装包括具有电路表面和与电路表面相对的后表面的集成电路管芯。 一层延性材料沉积在集成电路管芯的后表面上。

公开(公告)号：US07354790B2

公开(公告)日：2008-04-08

申请号：US11132751

申请日：2005-05-18

申请人： Parthasarathy Rajagopalan ,  Zafer Kutlu ,  Emery O. Sugasawara ,  Charles E. Vonderach ,  Dilip P. Vijay ,  Yogendra Ranade ,  Jeff Hall ,  Dwight Manning

发明人： Parthasarathy Rajagopalan ,  Zafer Kutlu ,  Emery O. Sugasawara ,  Charles E. Vonderach ,  Dilip P. Vijay ,  Yogendra Ranade ,  Jeff Hall ,  Dwight Manning

IPC分类号： H01L21/66

CPC分类号： H01L21/78 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.

摘要翻译： 一种用于避免集成电路管芯中的切割切屑的方法和装置包括：（a）提供用于在其上形成多个集成电路管芯的晶片; （b）在晶片上形成多个集成电路管芯; 以及（c）在晶片上的集成电路裸片之间形成锯路，以在集成电路管芯被切割锯分离时减轻晶片中的切割应力。

公开(公告)号：US07345245B2

公开(公告)日：2008-03-18

申请号：US10681554

申请日：2003-10-08

申请人： Anand Govind ,  Zafer Kutlu ,  Farshad Ghahghahi

发明人： Anand Govind ,  Zafer Kutlu ,  Farshad Ghahghahi

IPC分类号： H05K1/16

CPC分类号： H01L23/49838 ,  H01L23/49816 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor package for a die with improved thermal cycling reliability. A first layer of the package provides ball pads dispersed throughout. A second layer of the package provides signal traces. A high stress area associated with the corner of the dies is defined. Preferably the high stress area is defined as two ball pitches away from the corner of the die. Signal traces are routed away from the high stress area and in particular signal traces are routed away from the ball pads associated with the high stress to eliminate the cracks in the routed traces.

摘要翻译： 一种具有改善热循环可靠性的模具的半导体封装。 包装的第一层提供分散在其中的球垫。 封装的第二层提供信号迹线。 定义了与模具角部相关联的高应力区域。 优选地，高应力区域被定义为远离模具角部的两个球距。 信号迹线远离高应力区域，特别是信号迹线远离与高应力相关的球垫，以消除路由迹线中的裂纹。

公开(公告)号：US06639321B1

公开(公告)日：2003-10-28

申请号：US09680759

申请日：2000-10-06

申请人： Kumar Nagarajan ,  Zafer Kutlu ,  Shirish Shah

发明人： Kumar Nagarajan ,  Zafer Kutlu ,  Shirish Shah

IPC分类号： H01L2940

CPC分类号： H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A flip chip ball grid array package includes a thin die having a die thickness reduced from a wafer thickness to reduce mismatch of a coefficient of thermal expansion between the thin die and a substrate; a plurality of thin film layers formed on the thin die wherein each of the plurality of thin film layers has a coefficient of thermal expansion that is greater than that of the thin die and is less than that of the substrate; and a plurality of wafer bumps formed on the thin die for making electrical contact between the thin die and the substrate.

摘要翻译： 倒装芯片球栅阵列封装包括具有从晶片厚度减小的管芯厚度的薄管芯，以减少薄管芯和基板之间的热膨胀系数的失配; 多个薄膜层，其形成在所述薄模上，其中所述多个薄膜层中的每一个具有大于所述薄模的热膨胀系数，并且小于所述基板的热膨胀系数; 以及形成在薄模上的多个晶片凸块，用于在薄模和基板之间进行电接触。

公开(公告)号：US20060267615A1

公开(公告)日：2006-11-30

申请号：US11140455

申请日：2005-05-27

申请人： Carlo Grilletto ,  Zafer Kutlu

发明人： Carlo Grilletto ,  Zafer Kutlu

IPC分类号： G01R31/02

CPC分类号： G01R31/043 ,  G01R1/0433 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/09627 ,  H05K2201/10325 ,  H05K2201/10734 ,  H05K2203/162

摘要： A zero automated electrical testing (ATE) interposer daughter card (IDC) is provided for use in a test apparatus for ATE. Embodiments of the IDC include a first side having a first set of pads for mounting I/O's of a test package; and a second side having a second set of pads coupled to the first set of pads for replicating the first set of pads, wherein the second set of pads is located in area of the interposer card horizontally offset from the first set of pads, such that ATE measurements are obtained by removably inserting only a portion of the interposer card containing the second set of pads into an ATE test socket.

公开(公告)号：US20060160269A1

公开(公告)日：2006-07-20

申请号：US11132751

申请日：2005-05-18

申请人： Parthasarathy Rajagopalan ,  Zafer Kutlu ,  Emery Sugasawara ,  Charles Vonderach ,  Dilip Vijay ,  Yogendra Ranade ,  Jeff Hall ,  Dwight Manning

发明人： Parthasarathy Rajagopalan ,  Zafer Kutlu ,  Emery Sugasawara ,  Charles Vonderach ,  Dilip Vijay ,  Yogendra Ranade ,  Jeff Hall ,  Dwight Manning

IPC分类号： H01L21/50 ,  H01L21/78 ,  H01L23/02

CPC分类号： H01L21/78 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.

摘要翻译： 一种用于避免集成电路管芯中的切割切屑的方法和装置包括：（a）提供用于在其上形成多个集成电路管芯的晶片; （b）在晶片上形成多个集成电路管芯; 以及（c）在晶片上的集成电路裸片之间形成锯路，以在集成电路管芯被切割锯分离时减轻晶片中的切割应力。

公开(公告)号：US07190082B2

公开(公告)日：2007-03-13

申请号：US10396955

申请日：2003-03-24

申请人： Kumar Nagarajan ,  Zafer Kutlu

发明人： Kumar Nagarajan ,  Zafer Kutlu

IPC分类号： H01L23/29 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/563 ,  H01L23/295 ,  H01L2224/73203 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/00

摘要： An underfill includes a base material and a filler material added to the base material wherein the filler material constitutes a selected percentage by weight of the underfill to provide an optimum balance between interfacial die stress and solder bump strain for next generation, Cu, low-K silicon technology.

摘要翻译： 底部填充物包括添加到基材中的基材和填充材料，其中填充材料构成底部填充物的选定重量百分比，以在下一代Cu，低K下的界面模应力和焊料凸起应变之间提供最佳平衡 硅技术。

公开(公告)号：US20050077081A1

公开(公告)日：2005-04-14

申请号：US10681554

申请日：2003-10-08

申请人： Anand Govind ,  Zafer Kutlu ,  Farshad Ghahghahi

发明人： Anand Govind ,  Zafer Kutlu ,  Farshad Ghahghahi

IPC分类号： H01L23/498 ,  H05K1/11

CPC分类号： H01L23/49838 ,  H01L23/49816 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor package for a die with improved thermal cycling reliability. A first layer of the package provides ball pads dispersed throughout. A second layer of the package provides signal traces. A high stress area associated with the corner of the dies is defined. Preferably the high stress area is defined as two ball pitches away from the corner of the die. Signal traces are routed away from the high stress area and in particular signal traces are routed away from the ball pads associated with the high stress to eliminate the cracks in the routed traces.

摘要翻译： 一种具有改善热循环可靠性的模具的半导体封装。 包装的第一层提供分散在其中的球垫。 封装的第二层提供信号迹线。 定义了与模具角部相关联的高应力区域。 优选地，高应力区域被定义为远离模具角部的两个球距。 信号迹线远离高应力区域，特别是信号迹线远离与高应力相关联的球垫，以消除路线迹线中的裂纹。