公开(公告)号：US09691720B2

公开(公告)日：2017-06-27

申请号：US14809983

申请日：2015-07-27

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Uei-Ming Jow ,  Jong-Hoon Lee

IPC: H01L23/58 ,  H01L49/02 ,  H01L21/765

CPC classification number: H01L23/585 ,  H01L21/765 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A multi-layer ground shield structure of interconnected elements is disclosed. The ground shield structure may include a first patterned layer of a ground shield structure, a second patterned layer of the ground shield structure, and a spacer between the first patterned layer and the second patterned layer. The first patterned layer includes first conductive elements interconnected within the first patterned layer according to a first pattern. The second patterned layer includes second conductive elements interconnected within the second patterned layer according to a second pattern.

公开(公告)号：US09653533B2

公开(公告)日：2017-05-16

申请号：US14625484

申请日：2015-02-18

Applicant: QUALCOMM Incorporated

Inventor： Uei-Ming Jow ,  Young Kyu Song ,  Jong-Hoon Lee ,  Xiaonan Zhang

IPC: H01L23/52 ,  H01L49/02 ,  H01L23/522 ,  H01G4/33 ,  H01L23/64

CPC classification number: H01L28/86 ,  H01G4/33 ,  H01L23/5223 ,  H01L23/642 ,  H01L28/60

Abstract: An upper planar capacitor is spaced above a lower planar capacitor by a dielectric layer. A bridged-post inter-layer connector couples the capacitances in parallel, through first posts and second posts. The first posts and second posts extend through the dielectric layer, adjacent the upper and lower planar capacitors. A first level coupler extends under the dielectric layer and couples the first posts together and to a conductor of the lower planar capacitor, and couples another conductor of the lower planar capacitor to one of the second posts. A second level coupler extends above the dielectric layer, and couples the second posts together and to a conductor of the upper planar capacitor, and couples another conductor of the upper planar capacitor to one of the first posts.

公开(公告)号：US20160372253A1

公开(公告)日：2016-12-22

申请号：US14746652

申请日：2015-06-22

Applicant: QUALCOMM Incorporated

Inventor： Uei-Ming Jow ,  Young Kyu Song ,  Jong-Hoon Lee ,  Jung Ho Yoon ,  Sangjo Choi ,  Xiaonan Zhang

IPC: H01F27/28 ,  H01F41/04

CPC classification number: H01F27/2804 ,  H01F17/0006 ,  H01F17/0013 ,  H01F41/041 ,  H01F2027/2809

Abstract: An inductor structure includes a first set of traces corresponding to a first layer of an inductor, a second set of traces corresponding to a second layer of the inductor, and a third set of traces corresponding to a third layer of the inductor that is positioned between the first layer and the second layer. The first set of traces includes a first trace and a second trace that is parallel to the first trace. A dimension of the first trace is different from a corresponding dimension of the second trace. The second set of traces is coupled to the first set of traces. The second set of traces includes a third trace that is coupled to the first trace and to the second trace. The third set of traces is coupled to the first set of traces.

Abstract translation: 电感器结构包括对应于电感器的第一层的第一组迹线，对应于电感器的第二层的第二组迹线，以及对应于电感器的第三层的第三组迹线，其位于 第一层和第二层。 第一组轨迹包括与第一轨迹平行的第一轨迹和第二轨迹。 第一个跟踪的维度与第二个跟踪的相应维度不同。 第二组迹线耦合到第一组迹线。 第二组迹线包括耦合到第一迹线和第二迹线的第三迹线。 第三组迹线耦合到第一组迹线。

公开(公告)号：US20160240463A1

公开(公告)日：2016-08-18

申请号：US14703290

申请日：2015-05-04

Applicant: QUALCOMM Incorporated

Inventor： Uei-Ming Jow ,  Young Kyu Song ,  Jong-Hoon Lee ,  Xiaonan Zhang ,  Mario Francisco Velez

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/15311

Abstract: An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one dielectric layer, a first stack of first interconnects in the at least one dielectric layer, and a second interconnect formed on at least one side portion of the at least one dielectric layer. The first stack of first interconnects is configured to provide a first electrical path for a non-ground reference signal, where the first stack of first interconnects is located along at least one side of the package substrate. The second interconnect is configured to provide a second electrical path for a ground reference signal.

Abstract translation: 一种集成电路器件，包括封装衬底和耦合到封装衬底的管芯。 封装衬底包括至少一个电介质层，至少一个电介质层中的第一互连的第一叠层，以及形成在所述至少一个电介质层的至少一个侧部上的第二互连。 第一互连的第一堆叠被配置为提供用于非接地参考信号的第一电路径，其中第一互连的第一堆叠沿着封装衬底的至少一侧设置。 第二互连被配置为提供用于接地参考信号的第二电路径。

公开(公告)号：US09691694B2

公开(公告)日：2017-06-27

申请号：US14703290

申请日：2015-05-04

Applicant: QUALCOMM Incorporated

Inventor： Uei-Ming Jow ,  Young Kyu Song ,  Jong-Hoon Lee ,  Xiaonan Zhang ,  Mario Francisco Velez

IPC: H01L23/48 ,  H01L21/336 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/50

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/15311

Abstract: An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one dielectric layer, a first stack of first interconnects in the at least one dielectric layer, and a second interconnect formed on at least one side portion of the at least one dielectric layer. The first stack of first interconnects is configured to provide a first electrical path for a non-ground reference signal, where the first stack of first interconnects is located along at least one side of the package substrate. The second interconnect is configured to provide a second electrical path for a ground reference signal.

公开(公告)号：US09368566B2

公开(公告)日：2016-06-14

申请号：US14334521

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Jong-Hoon Lee ,  Young Kyu Song ,  Daeik Daniel Kim ,  Jung Ho Yoon ,  Uei-Ming Jow ,  Mario Francisco Velez ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L29/00 ,  H01L49/02 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L28/40 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: Some features pertain to an integrated device (e.g., package-on-package (PoP) device) that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer.

Abstract translation: 一些特征涉及包括衬底，第一管芯，第一封装层，第一再分配部分，第二管芯，第二封装层和第二封装层的集成器件（例如，封装封装（PoP）器件） 第二再分配部分。 基板包括第一表面和第二表面。 基板包括电容器。 第一管芯耦合到衬底的第一表面。 第一封装层封装第一裸片。 第一再分配部分耦合到第一封装。 第二管芯耦合到衬底的第二表面。 第二封装层封装第二管芯。 第二再分配部分耦合到第二封装层。

公开(公告)号：US09812752B2

公开(公告)日：2017-11-07

申请号：US15218626

申请日：2016-07-25

Applicant: QUALCOMM Incorporated

Inventor： John Jong-Hoon Lee ,  Young Kyu Song ,  Uei-Ming Jow ,  Sangjo Choi ,  Xiaonan Zhang

IPC: H01P1/20 ,  H01P7/06 ,  H01L21/00 ,  H01L27/15 ,  H01L23/66 ,  H01L49/02 ,  H03B5/18 ,  H01P1/201 ,  H01P1/207 ,  H01L23/552 ,  H01L21/48 ,  H01L23/522 ,  H01L23/60 ,  H01L23/00 ,  H05K1/02

CPC classification number: H01P1/207 ,  H01L21/4853 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/60 ,  H01L23/66 ,  H01L24/16 ,  H01L28/10 ,  H01L28/40 ,  H01L2223/6627 ,  H01L2223/6666 ,  H01L2223/6672 ,  H01L2224/10 ,  H01L2224/16227 ,  H01P1/201 ,  H01P7/06 ,  H01P7/065 ,  H03B5/1817 ,  H05K1/0243

Abstract: A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.

公开(公告)号：US09247647B1

公开(公告)日：2016-01-26

申请号：US14484000

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Jung Ho Yoon ,  Xiaonan Zhang ,  Jong-Hoon Lee ,  Young Kyu Song ,  Uei-Ming Jow

IPC: H01L29/00 ,  H05K1/18 ,  H01L23/498 ,  H01L49/02 ,  H03H7/01

CPC classification number: H01L28/40 ,  H01F17/0006 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2924/15311 ,  H05K1/112 ,  H05K1/116 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4688 ,  H05K2201/094 ,  H05K2201/096 ,  H05K2201/09672 ,  H05K2201/10734 ,  H01L2924/014

Abstract: A package substrate (or printed circuit board) that includes at least one dielectric layer, a first inductor structure is at least partially located in the dielectric layer, a third interconnect, and a second inductor structure. The first inductor structure includes a first interconnect, a first via coupled to the first interconnect, and a second interconnect coupled to the first via. The third interconnect is coupled to the first inductor structure. The third interconnect is configured to provide an electrical path for a ground signal. The second inductor structure is at least partially located in the dielectric layer. The second inductor is coupled to the third interconnect. The second inductor structure includes a fourth interconnect, a second via coupled to the fourth interconnect, and a fifth interconnect coupled to the second via. The first and second inductor structures are configured to operate with a capacitor as a 3rd harmonic suppression filter.

Abstract translation: 包括至少一个介电层的封装基板（或印刷电路板），第一电感结构至少部分地位于介电层，第三互连和第二电感结构中。 第一电感器结构包括第一互连，耦合到第一互连的第一通路和耦合到第一通路的第二互连。 第三互连件耦合到第一电感器结构。 第三互连被配置为提供用于接地信号的电路径。 第二电感器结构至少部分地位于电介质层中。 第二电感器耦合到第三互连。 第二电感器结构包括第四互连，耦合到第四互连的第二通路和耦合到第二通路的第五互连。 第一和第二电感器结构被配置为用作为三次谐波抑制滤波器的电容器操作。

公开(公告)号：US20160020193A1

公开(公告)日：2016-01-21

申请号：US14334521

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Jong-Hoon Lee ,  Young Kyu Song ,  Daeik Daniel Kim ,  Jung Ho Yoon ,  Uei-Ming Jow ,  Mario Francisco Velez ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L25/065 ,  H01L25/00 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: Some features pertain to an integrated device (e.g., package-on-package (PoP) device) that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer.

Abstract translation: 一些特征涉及包括衬底，第一管芯，第一封装层，第一再分配部分，第二管芯，第二封装层和第二封装层的集成器件（例如，封装封装（PoP）器件） 第二再分配部分。 基板包括第一表面和第二表面。 基板包括电容器。 第一管芯耦合到衬底的第一表面。 第一封装层封装第一裸片。 第一再分配部分耦合到第一封装。 第二管芯耦合到衬底的第二表面。 第二封装层封装第二管芯。 第二再分配部分耦合到第二封装层。

公开(公告)号：US10109584B2

公开(公告)日：2018-10-23

申请号：US14474860

申请日：2014-09-02

Applicant: QUALCOMM Incorporated

Inventor： Uei-Ming Jow ,  Young Kyu Song ,  Jung Ho Yoon ,  Jong-Hoon Lee ,  Xiaonan Zhang

IPC: H01F17/00 ,  H01F27/28 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/64 ,  H01L49/02 ,  H01L23/495 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor package according to some examples of the disclosure may include a first body layer, a transformer that may comprise one or more inductors, coupled inductors, or inductive elements positioned above the first body layer. A first ground plane is on a top of the first body layer between the first body layer and the inductive element. The first ground plane may have conductive lines generally perpendicular to a magnetic field generated by the inductive element, and a second ground plane on a bottom of the first body layer opposite the first ground plane. The first and second ground planes may also provide heat dissipation elements for the semiconductor as well as reduce or eliminate eddy current and parasitic effects produced by the inductive element.