公开(公告)号：US08900988B2

公开(公告)日：2014-12-02

申请号：US13088083

申请日：2011-04-15

申请人： Qinghuang Lin ,  Benjamin L. Fletcher ,  Cyril Cabral, Jr.

发明人： Qinghuang Lin ,  Benjamin L. Fletcher ,  Cyril Cabral, Jr.

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L23/5222 ,  H01L21/31127 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/4821 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： Devices and methods for forming a self-aligned airgap interconnect structure includes etching a conductive layer to a substrate to form conductive structures with patterned gaps and filling the gaps with a sacrificial material. The sacrificial material is planarized to expose a top surface of the conductive layer. A permeable cap layer is deposited over the conductive structure and the sacrificial material. Self-aligned airgaps are formed by removing the sacrificial material through the permeable layer.

摘要翻译： 用于形成自对准气隙互连结构的装置和方法包括将导电层蚀刻到衬底以形成具有图案化间隙的导电结构并用牺牲材料填充间隙。 将牺牲材料平坦化以暴露导电层的顶表面。 在导电结构和牺牲材料上沉积可渗透盖层。 通过可渗透层去除牺牲材料形成自对准的气隙。

公开(公告)号：US08362600B2

公开(公告)日：2013-01-29

申请号：US12689268

申请日：2010-01-19

申请人： Cyril Cabral, Jr. ,  Michael S. Gordon ,  David F. Heidel ,  Conal Eugene Murray ,  Kenneth Parker Rodbell ,  Henry Hong Ki Tang

发明人： Cyril Cabral, Jr. ,  Michael S. Gordon ,  David F. Heidel ,  Conal Eugene Murray ,  Kenneth Parker Rodbell ,  Henry Hong Ki Tang

IPC分类号： H01L23/556 ,  H01L21/60

CPC分类号： H01L23/556 ,  H01L24/13 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00

摘要： A method is disclosed that includes providing a semiconductor substrate having one or more device levels including a number of devices, and forming a number of wiring levels on a top surface of the one or more device levels, wherein one or more of the number of wiring levels includes one or more alpha particle blocking shields situated between at least one of the number of devices and a predetermined first location where a terminal pad will be formed in one of the wiring levels, the one or more alpha particle blocking shields placed at a second location, having one or more widths, and occupying a predetermined number of the wiring levels, sufficient to prevent a predetermined percentage of alpha particles of a selected energy or less expected to be emitted from an alpha particle emitting metallization to be formed adjacent and connected to the terminal pad from reaching the one device.

摘要翻译： 公开了一种方法，其包括提供具有包括多个器件的一个或多个器件电平的半导体衬底，以及在所述一个或多个器件级的顶表面上形成多个布线电平，其中所述多个布线中的一个或多个 水平包括一个或多个α粒子阻挡屏蔽，位于多个器件中的至少一个与预定的第一位置之间，其中端子焊盘将形成在一个布线层中，一个或多个α粒子阻挡屏蔽放置在第二个 位置，具有一个或多个宽度并且占据预定数量的布线水平，足以防止预定百分比的α粒子被选择的能量或预期从发射的α粒子发射的金属化物发射出来邻近并连接到 终端垫到达一个设备。

公开(公告)号：US08193051B2

公开(公告)日：2012-06-05

申请号：US13047172

申请日：2011-03-14

申请人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

公开(公告)号：US08129267B2

公开(公告)日：2012-03-06

申请号：US12052881

申请日：2008-03-21

申请人： Cyril Cabral, Jr. ,  K. Paul Muller ,  Kenneth P. Rodbell

发明人： Cyril Cabral, Jr. ,  K. Paul Muller ,  Kenneth P. Rodbell

IPC分类号： H01L21/4763

CPC分类号： H01L23/5223 ,  H01L23/3192 ,  H01L23/53238 ,  H01L23/556 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/02166 ,  H01L2224/03831 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/10125 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13007 ,  H01L2224/13028 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13487 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/05552 ,  H01L2924/00

摘要： An alpha particle blocking structure and method of making the structure. The structure includes: a semiconductor substrate; a set of interlevel dielectric layers stacked from a lowermost interlevel dielectric layer closest to the substrate to a uppermost interlevel dielectric layer furthest from the substrate, each interlevel dielectric layer of the set of interlevel dielectric layers including electrically conductive wires, top surfaces of the wires substantially coplanar with top surfaces of corresponding interlevel dielectric layers; an electrically conductive tot final pad contacting a wire pad of the uppermost interlevel dielectric layer; an electrically conductive plating base layer contacting a top surface of the terminal pad; and a copper block on the plating base layer.

摘要翻译： 一种α粒子阻挡结构及其制造方法。 该结构包括：半导体衬底; 一组层间电介质层，从最靠近衬底的最下层的层间电介质层堆叠到距离衬底最远的最上层的层间电介质层，层间电介质层组中的每个层间电介质层包括导电线，电线的顶表面基本上 与对应的层间电介质层的顶表面共面; 接触最上面的层间电介质层的焊盘的导电的最终焊盘; 与所述端子焊盘的顶表面接触的导电电镀基层; 以及镀覆基底层上的铜块。

公开(公告)号：US08008199B2

公开(公告)日：2011-08-30

申请号：US12869113

申请日：2010-08-26

申请人： Brett C. Baker-O'Neal ,  Cyril Cabral, Jr. ,  Qiang Huang ,  Kenneth P. Rodbell

发明人： Brett C. Baker-O'Neal ,  Cyril Cabral, Jr. ,  Qiang Huang ,  Kenneth P. Rodbell

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/76873 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10% of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line.

摘要翻译： 为了改变铜线和通孔的微观结构，将钴添加到铜种子层，铜镀层或铜覆盖层。 钴可以是铜 - 钴合金的形式或作为非常薄的钴层。 本发明金属互连结构中竹结构中晶界的结构关闭了铜晶界扩散。 晶粒生长后的金属互连结构的组成含有约1ppm至约10原子浓度的钴。 晶粒边界从铜 - 钴合金线的顶表面延伸到铜 - 钴合金线的底表面，并且与任何其它晶界分开大于铜 - 钴合金线的宽度的距离。

公开(公告)号：US07843063B2

公开(公告)日：2010-11-30

申请号：US12031103

申请日：2008-02-14

申请人： Brett C. Baker-O'Neal ,  Cyril Cabral, Jr. ,  Qiang Huang ,  Kenneth P. Rodbell

发明人： Brett C. Baker-O'Neal ,  Cyril Cabral, Jr. ,  Qiang Huang ,  Kenneth P. Rodbell

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76877 ,  H01L21/76873 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10% of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line.

摘要翻译： 为了改变铜线和通孔的微观结构，将钴添加到铜种子层，铜镀层或铜覆盖层。 钴可以是铜 - 钴合金的形式或作为非常薄的钴层。 本发明金属互连结构中竹结构中晶界的结构关闭了铜晶界扩散。 晶粒生长后的金属互连结构的组成含有约1ppm至约10原子浓度的钴。 晶粒边界从铜 - 钴合金线的顶表面延伸到铜 - 钴合金线的底表面，并且与任何其它晶界分开大于铜 - 钴合金线的宽度的距离。

公开(公告)号：US07682968B2

公开(公告)日：2010-03-23

申请号：US12108001

申请日：2008-04-23

申请人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Christophe Detavernier ,  Simon Gaudet ,  Christian Lavoie ,  Huiling Shang

发明人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Christophe Detavernier ,  Simon Gaudet ,  Christian Lavoie ,  Huiling Shang

IPC分类号： H01L21/44

CPC分类号： H01L21/28525 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

摘要： A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate.

摘要翻译： 提供了一种形成锗硅化物的方法，该方法与由纯金属形成的常规硅化物接触相比更能抵抗蚀刻的含Ge层顶部接触。 本发明的方法包括首先提供一种结构，该结构包括位于其中具有源极/漏极区域的含Ge衬底顶部的多个栅极区域。 在本发明的该步骤之后，在所述含Ge基材上形成含Si金属层。 在暴露的区域中，含Ge衬底与含Si金属层接触。 然后进行退火以在含Si金属层和含Ge基板接触的区域中形成锗化硅化合物; 此后，使用选择性蚀刻工艺从结构中除去任何未反应的含Si金属层。 在一些实施方案中，附加的退火步骤可以跟随去除步骤。 本发明的方法提供了一种在含Ge衬底顶上具有锗硅化物接触层的结构，其中锗硅化物接触层含有比下面的含Ge衬底更多的Si。

公开(公告)号：US07667278B2

公开(公告)日：2010-02-23

申请号：US11372140

申请日：2006-03-10

申请人： Cyril Cabral, Jr. ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine L. Saenger

发明人： Cyril Cabral, Jr. ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine L. Saenger

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/06 ,  H01L29/12

CPC分类号： H01L29/4966 ,  H01L21/823842

摘要： A semiconductor device such as a complementary metal oxide semiconductor (CMOS) including at least one FET that includes a gate electrode including a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.

摘要翻译： 提供了包括包括包括金属碳化物的栅电极和至少一种制造方法的至少一个FET的互补金属氧化物半导体（CMOS）的半导体器件。 CMOS包括双功能金属栅电极，由此双功能功能由金属和金属的碳化物提供。

公开(公告)号：US07326610B2

公开(公告)日：2008-02-05

申请号：US11271032

申请日：2005-11-10

申请人： Ricky S. Amos ,  Douglas A. Buchanan ,  Cyril Cabral, Jr. ,  Evgeni P. Gousev ,  Victor Ku ,  An Steegen

发明人： Ricky S. Amos ,  Douglas A. Buchanan ,  Cyril Cabral, Jr. ,  Evgeni P. Gousev ,  Victor Ku ,  An Steegen

IPC分类号： H01L21/31

CPC分类号： H01L21/823842 ,  H01L21/76895 ,  H01L21/823835

摘要： Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds. A second silicide may be employed within the gate. A replacement gate is made from two different metals (dual metal gate replacement) prior to capping with a silicide.

摘要翻译： 硅化物通过不同的工艺选择被引入到CMOS器件的栅极区域，用于常规和替代栅极类型工艺。 将硅化物放置在栅极本身中，引入硅化物直接与栅极电介质接触，将硅化物作为填充物引入金属栅极顶部，并准备就绪，并将硅化物作为覆盖层引入到多晶硅上或 现有的金属门。 硅化物用作连接CMOS结构的PFET和NFET器件的选项。 该过程保护金属栅极，同时允许源极和漏极硅化物与栅极硅化物不同的硅化物。 提供了具有栅极和源极和漏极区域的半导体衬底。 栅极电介质层与金属栅极层一起沉积在衬底上。 然后用形成在栅极顶部上的硅化物对金属栅极层进行封装，然后继续进行常规的器件形成。 可以在栅极内使用第二硅化物。 在使用硅化物封盖之前，更换栅极由两种不同的金属（双金属栅极替代）制成。

公开(公告)号：US07271486B2

公开(公告)日：2007-09-18

申请号：US11075289

申请日：2005-03-08

申请人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Christophe Detavernier ,  James M. E. Harper ,  Christian Lavoie

发明人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Christophe Detavernier ,  James M. E. Harper ,  Christian Lavoie

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： C04B35/58 ,  C04B35/58085 ,  C04B2235/40 ,  C04B2235/404 ,  C04B2235/405 ,  C04B2235/408 ,  C23C26/00 ,  C23C30/00 ,  H01L21/28518 ,  H01L21/76889

摘要： A method for providing a low resistance non-agglomerated Ni monosilicide contact that is useful in semiconductor devices. Where the inventive method of fabricating a substantially non-agglomerated Ni alloy monosilicide comprises the steps of: forming a metal alloy layer over a portion of a Si-containing substrate, wherein said metal alloy layer comprises of Ni and one or multiple alloying additive(s), where said alloying additive is Ti, V, Ge, Cr, Zr, Nb, Mo, Hf, Ta, W, Re, Rh, Pd or Pt or mixtures thereof; annealing the metal alloy layer at a temperature to convert a portion of said metal alloy layer into a Ni alloy monosilicide layer; and removing remaining metal alloy layer not converted into Ni alloy monosilicide. The alloying additives are selected for phase stability and to retard agglomeration. The alloying additives most efficient in retarding agglomeration are most efficient in producing silicides with low sheet resistance.

摘要翻译： 一种用于提供半导体器件中有用的低电阻非聚集Ni单硅化物接触的方法。 在制造基本上非团聚的Ni合金一硅化硅的本发明方法中，包括以下步骤：在含Si衬底的一部分上形成金属合金层，其中所述金属合金层包括Ni和一种或多种合金添加剂 ），其中所述合金添加剂为Ti，V，Ge，Cr，Zr，Nb，Mo，Hf，Ta，W，Re，Rh，Pd或Pt或其混合物; 在将所述金属合金层的一部分转化为Ni合金一硅化物层的温度下退火金属合金层; 并且除去未转化为Ni合金一硅化物的剩余金属合金层。 选择合金添加剂用于相稳定性并阻止团聚。 延迟聚集中最有效的合金添加剂在生产低薄层电阻的硅化物中是最有效的。