公开(公告)号：US10115469B2

公开(公告)日：2018-10-30

申请号：US15796193

申请日：2017-10-27

Applicant: Renesas Electronics Corporation

Inventor： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC: G11C16/26 ,  G11C5/02 ,  H01L29/788 ,  G11C8/08 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  G11C16/04

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

公开(公告)号：US09170637B2

公开(公告)日：2015-10-27

申请号：US14685349

申请日：2015-04-13

Applicant: Renesas Electronics Corporation

Inventor： Mamoru Sakugawa ,  Masamichi Fujito ,  Jun Setogawa ,  Masaru Takahashi ,  Shinsuke Yoshimura

IPC: G06F1/32 ,  G06F1/08

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A data processing device, includes a central processing unit configured to operate in accordance with a program; a register capable of setting a first mode and a second mode; a non-volatile memory; a sequencer configured to control the non-volatile memory; and a first clock circuit for supplying a first clock to the central processing unit and the non-volatile memory, wherein the first mode is a mode in which the central processing unit is operated within a first range of an external supply voltage, wherein the second mode is a mode in which the central processing unit is operated within a second range of the external supply voltage, the second range includes the first range and a relatively low voltage lower than the lower limit voltage of the first range.

Abstract translation: 一种数据处理装置，包括：中央处理单元，被配置为根据程序进行操作; 能够设置第一模式和第二模式的寄存器; 非易失性存储器; 配置成控制所述非易失性存储器的定序器; 以及第一时钟电路，用于向中央处理单元和非易失性存储器提供第一时钟，其中第一模式是中央处理单元在外部电源电压的第一范围内操作的模式，其中第二时钟 模式是中央处理单元在外部电源电压的第二范围内操作的模式，第二范围包括低于第一范围的下限电压的第一范围和相对低的电压。

公开(公告)号：US10249638B2

公开(公告)日：2019-04-02

申请号：US15904349

申请日：2018-02-24

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro Yamashita ,  Tamotsu Ogata ,  Masamichi Fujito ,  Tomoya Saito

IPC: H01L27/11568 ,  H01L27/11573 ,  H01L49/02

Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.

公开(公告)号：US09812211B2

公开(公告)日：2017-11-07

申请号：US15224669

申请日：2016-08-01

Applicant: Renesas Electronics Corporation

Inventor： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC: G11C16/10 ,  G11C16/26 ,  H01L21/28 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  G11C16/24 ,  G11C5/02 ,  G11C8/08 ,  G11C16/08 ,  G11C16/30 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

公开(公告)号：US09747990B2

公开(公告)日：2017-08-29

申请号：US15167596

申请日：2016-05-27

Applicant: Renesas Electronics Corporation

Inventor： Masamichi Fujito ,  Hiroshi Yoshida ,  Takanori Takahashi ,  Yasuhiko Taito

IPC: G11C16/20 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/20 ,  G11C16/0416 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3459 ,  G11C16/3481

Abstract: A semiconductor device includes a memory array having a plurality of complementary cells, each including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, and a control circuit for initializing the complementary cells. The control circuit performs a first initialization control of reducing the threshold voltage of both the first memory element and the second memory element of the complementary cell and changing the threshold voltage of at least one of the first memory element and the second memory element at an intermediate level lower than a first writing level and higher than an initialization level, a first writing control of changing the threshold voltage of one of the first memory element and the second memory element of the complementary cell at the first writing level, and a second initialization control of changing the threshold voltage of both the first memory element and the second memory element of the complementary cell at the initialization level.

公开(公告)号：US10354735B2

公开(公告)日：2019-07-16

申请号：US16116893

申请日：2018-08-29

Applicant: Renesas Electronics Corporation

Inventor： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC: G11C16/26 ,  G11C16/04 ,  H01L21/28 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  G11C16/24 ,  G11C5/02 ,  G11C8/08 ,  G11C16/08 ,  G11C16/30

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

公开(公告)号：US20170330630A1

公开(公告)日：2017-11-16

申请号：US15667487

申请日：2017-08-02

Applicant: Renesas Electronics Corporation

Inventor： Masamichi Fujito ,  Hiroshi Yoshida ,  Takanori Takahashi ,  Yasuhiko Taito

IPC: G11C16/20 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34

CPC classification number: G11C16/20 ,  G11C16/0416 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3459 ,  G11C16/3481

Abstract: A controlling method of a semiconductor device provided with a memory array including a plurality of complementary cells, each cell including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, the controlling method comprising: performing a prewrite procedure that writes ‘0’ or ‘1’ to both of the first memory element and the second memory element.

公开(公告)号：US10031792B2

公开(公告)日：2018-07-24

申请号：US15650282

申请日：2017-07-14

Applicant: Renesas Electronics Corporation

Inventor： Tomoya Saito ,  Masamichi Fujito ,  Koichi Ando ,  Takashi Hashimoto

IPC: G11C7/00 ,  G06F11/07

Abstract: The present invention aims at providing a flash memory that can perform a refresh operation at an appropriate time before a read error occurs. The controller performs the first read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the first speed, and concurrently, the sense amplifier is made to read data; the second read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the second speed faster than the first speed, and concurrently, the sense amplifier is made to read data; and the refresh operation in which, when the data read by the first read operation and the data read by the second read operation are determined to be different, the data stored in the memory cell as the read target is rewritten.

公开(公告)号：US09412459B2

公开(公告)日：2016-08-09

申请号：US14214969

申请日：2014-03-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC: G11C16/26 ,  H01L21/28 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

公开(公告)号：US10559581B2

公开(公告)日：2020-02-11

申请号：US16269797

申请日：2019-02-07

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro Yamashita ,  Tamotsu Ogata ,  Masamichi Fujito ,  Tomoya Saito

IPC: H01L21/28 ,  H01L27/11573 ,  H01L49/02 ,  H01L27/11568 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L27/06 ,  H01L29/78 ,  H01L29/792 ,  H01L29/94 ,  H01L27/1157 ,  H01L29/417

Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.