公开(公告)号：US07928553B2

公开(公告)日：2011-04-19

申请号：US12848612

申请日：2010-08-02

申请人： Ralf Otremba ,  Oliver Haeberlen ,  Klaus Schiess

发明人： Ralf Otremba ,  Oliver Haeberlen ,  Klaus Schiess

IPC分类号： H01L23/22 ,  H01L21/00

CPC分类号： H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/24226 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82102 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/12032 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00

摘要： An electronic device and method is disclosed. In one embodiment, a method includes providing an electrically insulating substrate. A first electrically conductive layer is applied over the electrically insulating substrate. A first semiconductor chip is placed over the first electrically conductive layer. The first semiconductor chip comprises a first electrode on a first main surface and a second electrode on a second main surface. An electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the electrically insulating layer. A through connection is provided in the electrically insulating layer to couple the first electrically conductive layer to the second electrically conductive layer.

摘要翻译： 公开了一种电子设备和方法。 在一个实施例中，一种方法包括提供电绝缘基板。 将第一导电层施加在电绝缘基板上。 第一半导体芯片放置在第一导电层上。 第一半导体芯片包括第一主表面上的第一电极和第二主表面上的第二电极。 电绝缘层施加在第一导电层上。 在电绝缘层上施加第二导电层。 在电绝缘层中提供通孔连接以将第一导电层耦合到第二导电层。

公开(公告)号：US20100295171A1

公开(公告)日：2010-11-25

申请号：US12848612

申请日：2010-08-02

申请人： Ralf Otremba ,  Oliver Haeberlen ,  Klaus Schiess

发明人： Ralf Otremba ,  Oliver Haeberlen ,  Klaus Schiess

IPC分类号： H01L23/12

CPC分类号： H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/24226 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82102 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/12032 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00

摘要： An electronic device and method is disclosed. In one embodiment, a method includes providing an electrically insulating substrate. A first electrically conductive layer is applied over the electrically insulating substrate. A first semiconductor chip is placed over the first electrically conductive layer. An electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the electrically insulating layer.

摘要翻译： 公开了一种电子设备和方法。 在一个实施例中，一种方法包括提供电绝缘基板。 将第一导电层施加在电绝缘基板上。 第一半导体芯片放置在第一导电层上。 电绝缘层施加在第一导电层上。 在电绝缘层上施加第二导电层。

公开(公告)号：US07799614B2

公开(公告)日：2010-09-21

申请号：US11962883

申请日：2007-12-21

申请人： Ralf Otremba ,  Oliver Haeberlen ,  Klaus Schiess

发明人： Ralf Otremba ,  Oliver Haeberlen ,  Klaus Schiess

IPC分类号： H01L21/00 ,  H01L23/34 ,  H05K7/12

CPC分类号： H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/24226 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82102 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/12032 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00

摘要： An electronic device and method is disclosed. In one embodiment, a method includes providing an electrically insulating substrate. A first electrically conductive layer is applied over the electrically insulating substrate. A first semiconductor chip is placed over the first electrically conductive layer. An electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the electrically insulating layer. A through connection is formed in the electrically insulating layer to couple the second electrically conductive layer to the first electrically conductive layer.

摘要翻译： 公开了一种电子设备和方法。 在一个实施例中，一种方法包括提供电绝缘基板。 将第一导电层施加在电绝缘基板上。 第一半导体芯片放置在第一导电层上。 电绝缘层施加在第一导电层上。 在电绝缘层上施加第二导电层。 在电绝缘层中形成直通连接，以将第二导电层耦合到第一导电层。

公开(公告)号：US20090160046A1

公开(公告)日：2009-06-25

申请号：US11962883

申请日：2007-12-21

申请人： Ralf Otremba ,  Oliver Haeberlen ,  Klaus Schiess

发明人： Ralf Otremba ,  Oliver Haeberlen ,  Klaus Schiess

IPC分类号： H01L23/485 ,  H01L21/58

CPC分类号： H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/24226 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82102 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/12032 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00

摘要： An electronic device and method is disclosed. In one embodiment, a method includes providing an electrically insulating substrate. A first electrically conductive layer is applied over the electrically insulating substrate. A first semiconductor chip is placed over the first electrically conductive layer. An electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the electrically insulating layer.

摘要翻译： 公开了一种电子设备和方法。 在一个实施例中，一种方法包括提供电绝缘基板。 将第一导电层施加在电绝缘基板上。 第一半导体芯片放置在第一导电层上。 电绝缘层施加在第一导电层上。 在电绝缘层上施加第二导电层。

公开(公告)号：US07233059B2

公开(公告)日：2007-06-19

申请号：US10850157

申请日：2004-05-20

申请人： Nikolaus Bott ,  Oliver Haeberlen ,  Manfred Kotek ,  Joost Larik ,  Josef Maerz ,  Ralf Otremba

发明人： Nikolaus Bott ,  Oliver Haeberlen ,  Manfred Kotek ,  Joost Larik ,  Josef Maerz ,  Ralf Otremba

IPC分类号： H01L23/02 ,  H01L23/053 ,  H01L23/12 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L23/3192 ,  H01L24/05 ,  H01L25/16 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

摘要： The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.

摘要翻译： 本发明涉及通过至少一个钝化层彼此电绝缘的至少两个半导体部件的垂直布置。 本发明同样涉及制造这种半导体装置的方法。 规定了一种半导体装置，其中特别地，例如由热机械载荷引起的金属化边缘处的开裂风险降低，制造规定的高含量的自由基氢被最小化。 此外，规定了制造这种半导体装置的方法。

公开(公告)号：US07498194B2

公开(公告)日：2009-03-03

申请号：US11733930

申请日：2007-04-11

申请人： Nikolaus Bott ,  Oliver Haeberlen ,  Manfred Kotek ,  Joost Larik ,  Josef Maerz ,  Ralf Otremba

发明人： Nikolaus Bott ,  Oliver Haeberlen ,  Manfred Kotek ,  Joost Larik ,  Josef Maerz ,  Ralf Otremba

IPC分类号： H01L21/44

CPC分类号： H01L23/3192 ,  H01L24/05 ,  H01L25/16 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

摘要： The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.

摘要翻译： 本发明涉及通过至少一个钝化层彼此电绝缘的至少两个半导体部件的垂直布置。 本发明同样涉及制造这种半导体装置的方法。 规定了一种半导体装置，其中特别地，例如由热机械载荷引起的金属化边缘处的开裂风险降低，制造规定的高含量的自由基氢被最小化。 此外，规定了制造这种半导体装置的方法。

公开(公告)号：US20050012215A1

公开(公告)日：2005-01-20

申请号：US10850157

申请日：2004-05-20

申请人： Nikolaus Bott ,  Oliver Haeberlen ,  Manfred Kotek ,  Joost Larik ,  Josef Maerz ,  Ralf Otremba

发明人： Nikolaus Bott ,  Oliver Haeberlen ,  Manfred Kotek ,  Joost Larik ,  Josef Maerz ,  Ralf Otremba

IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L23/495

CPC分类号： H01L23/3192 ,  H01L24/05 ,  H01L25/16 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

摘要： The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.

摘要翻译： 本发明涉及通过至少一个钝化层彼此电绝缘的至少两个半导体部件的垂直布置。 本发明同样涉及制造这种半导体装置的方法。 规定了一种半导体装置，其中特别地，例如由热机械载荷引起的金属化边缘处的开裂风险降低，并且制造规定的高含量的自由基氢被最小化。 此外，规定了制造这种半导体装置的方法。

公开(公告)号：US20070178624A1

公开(公告)日：2007-08-02

申请号：US11733930

申请日：2007-04-11

申请人： Nikolaus Bott ,  Oliver Haeberlen ,  Manfred Kotek ,  Joost Larik ,  Josef Maerz ,  Ralf Otremba

发明人： Nikolaus Bott ,  Oliver Haeberlen ,  Manfred Kotek ,  Joost Larik ,  Josef Maerz ,  Ralf Otremba

IPC分类号： H01L21/00 ,  H01L21/4763

CPC分类号： H01L23/3192 ,  H01L24/05 ,  H01L25/16 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

摘要： The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.

摘要翻译： 本发明涉及通过至少一个钝化层彼此电绝缘的至少两个半导体部件的垂直布置。 本发明同样涉及制造这种半导体装置的方法。 规定了一种半导体装置，其中特别地，例如由热机械载荷引起的金属化边缘处的开裂风险降低，制造规定的高含量的自由基氢被最小化。 此外，规定了制造这种半导体装置的方法。

公开(公告)号：US20140001480A1

公开(公告)日：2014-01-02

申请号：US13540469

申请日：2012-07-02

申请人： Ralf Otremba ,  Klaus Schiess

发明人： Ralf Otremba ,  Klaus Schiess

IPC分类号： H01L23/495 ,  H01L21/28

CPC分类号： H01L23/3107 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29078 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40247 ,  H01L2224/40499 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92157 ,  H01L2224/92246 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/06 ,  H01L2924/014 ,  H01L2224/05599 ,  H01L2924/00012

摘要： In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip disposed over a lead frame, and a clip disposed over the semiconductor chip. A major surface of the semiconductor chip includes a contact pad and a control contact pad. The contact pad has a first portion along a first side of the control contact pad and a second portion along an opposite second side of the control contact pad. The clip electrically couples the first portion and the second portion with a first lead of the lead frame. A wire bond electrically couples the control contact pad with a second lead of the lead frame.

摘要翻译： 根据本发明的实施例，半导体器件包括设置在引线框架上的半导体芯片和设置在半导体芯片上的夹子。 半导体芯片的主表面包括接触焊盘和控制接触焊盘。 接触焊盘具有沿着控制接触焊盘的第一侧的第一部分和沿着控制接触焊盘的相对的第二侧的第二部分。 夹子用引线框架的第一引线电耦合第一部分和第二部分。 引线接合将控制接触焊盘与引线框架的第二引线电连接。

公开(公告)号：US08084816B2

公开(公告)日：2011-12-27

申请号：US12403000

申请日：2009-03-12

申请人： Ralf Otremba ,  Josef Hoeglauer ,  Klaus Schiess

发明人： Ralf Otremba ,  Josef Hoeglauer ,  Klaus Schiess

IPC分类号： H01L23/48 ,  H01L29/78

CPC分类号： H01L23/3107 ,  H01L21/561 ,  H01L21/6835 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L2221/68359 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/76155 ,  H01L2224/82005 ,  H01L2224/82102 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00

摘要： A semiconductor module is disclosed. One embodiment provides a first semiconductor chip having a first contact pad on a first main surface and a second contact pad on a second main surface, a first electrically conductive layer applied to the first main surface, a second electrically conductive layer applied to the second main surface, and an electrically insulating material covering the first electrically conductive layer, wherein a surface of the second electrically conductive layer forms an external contact pad and the second electrically conductive layer has a thickness of less than 200 μm.