公开(公告)号：US20240352275A1

公开(公告)日：2024-10-24

申请号：US18684930

申请日：2022-08-24

Applicant: Resonac Corporation

Inventor： Yuki IMAZU ,  Masaya TOBA ,  Yu AOKI ,  Yoshimi HAMANO

IPC: C09D163/04 ,  C09D125/16 ,  C09D179/08 ,  H01L21/768

CPC classification number: C09D163/04 ,  C09D125/16 ,  C09D179/08 ,  H01L21/76873

Abstract: A semiconductor device production method including: applying a resin composition onto a substrate and drying the resin composition to form a resin film; heating the resin film to obtain a cured resin film; forming a metal seed layer by sputtering on a surface of the cured resin film; forming a resist pattern having an opening portion for forming a wiring pattern on a surface of the metal seed layer; forming a metal layer having a wiring pattern with a wiring width of 3 μm or less and an inter-wiring distance of 3 μm or less by electrolytic plating in a region on the surface of the metal seed layer exposed from the resist pattern; removing the resist pattern; and removing the metal seed layer exposed by the removal of the resist pattern, wherein a cross-linking density of the cured resin film is 0.1×10−3 to 110×10−3 mol/cm3.

公开(公告)号：US20240341039A1

公开(公告)日：2024-10-10

申请号：US18294158

申请日：2022-07-29

Applicant: Resonac Corporation

Inventor： Kei TOGASAKI ,  Kazuyuki MITSUKURA ,  Masaya TOBA ,  Kenichi IWASHITA ,  Keishi ONO ,  Mao NARITA

IPC: H05K3/10 ,  C25D3/38 ,  C25D5/00 ,  C25D5/02 ,  C25D7/12 ,  H01L21/48 ,  H01L23/498 ,  H05K1/02

CPC classification number: H05K3/10 ,  C25D3/38 ,  C25D5/022 ,  C25D5/605 ,  C25D7/123 ,  H05K1/02 ,  H01L21/4846 ,  H01L23/49866 ,  H05K2203/11

Abstract: A method for manufacturing a wiring board, including: forming a resist layer on a seed layer comprising a metal provided on a support body; forming a pattern including an opening to which the seed layer is exposed in the resist layer by light exposure and development of the resist layer, and forming a copper plating layer on the seed layer exposed into the opening by electrolytic plating, in this order. The arithmetic mean roughness Ra of the surface of the seed layer on a side opposite to the support body is 0.05 μm or more and 0.30 μm or less.

公开(公告)号：US20240304462A1

公开(公告)日：2024-09-12

申请号：US18569217

申请日：2022-06-15

Applicant: Resonac Corporation

Inventor： Masaya TOBA ,  Masaki YAMAGUCHI

IPC: H01L21/48 ,  C23C18/16 ,  C23C18/38 ,  C23C28/02 ,  C25D3/38 ,  C25D5/02 ,  C25D7/12 ,  H01L23/12 ,  H05K1/03 ,  H05K3/18

CPC classification number: H01L21/4857 ,  C23C18/1641 ,  C23C18/1653 ,  C23C18/38 ,  C23C28/023 ,  C25D3/38 ,  C25D5/022 ,  C25D7/123 ,  H01L23/12 ,  H05K1/0366 ,  H05K3/188 ,  H05K2203/107

Abstract: A method for manufacturing a wiring board includes steps of: (I) forming an insulation material layer on a surface of a support substrate; (II) forming a first conductive layer on a surface of the insulation material layer by electroless copper plating; (III) forming a first opening passing through the first conductive layer and the insulation material layer; (IV) forming a second conductive layer on a surface of the first conductive layer and on a bottom surface and a side surface of the first opening by electroless copper plating; (V) forming a resist pattern having a second opening communicating with the first opening on a surface of the second conductive layer; and (VI) filling the first opening and the second opening with a conductive material including copper by electrolytic copper plating.

公开(公告)号：US20240049395A1

公开(公告)日：2024-02-08

申请号：US18258556

申请日：2020-12-25

Applicant: Resonac Corporation

Inventor： Masaya TOBA ,  Kazuyuki MITSUKURA ,  Masaki YAMAGUCHI

IPC: H05K1/18 ,  H05K3/02

CPC classification number: H05K1/181 ,  H05K3/022 ,  H05K2201/10553 ,  H05K2201/0358 ,  H05K2203/1377 ,  H05K2201/0209

Abstract: A layered plate including a copper layer having a thickness of 5 μm or less, and a resin layer provided on a surface of the copper layer, in which a water absorption rate of the resin layer is 1% or less after being left in an environment of 130° C. in temperature and 85% in relative humidity for 200 hours.

公开(公告)号：US20240397635A1

公开(公告)日：2024-11-28

申请号：US18791515

申请日：2024-08-01

Applicant: RESONAC CORPORATION

Inventor： Masaya TOBA ,  Kazuyuki MITSUKURA

IPC: H05K3/38 ,  H01L21/48 ,  H01L23/498 ,  H05K1/09 ,  H05K3/18 ,  H05K3/46

Abstract: A method for manufacturing a wiring structure includes forming a wiring on an insulating resin layer, which includes forming a modified region including pores in a surface layer of the insulating resin layer by treating a surface of the insulating resin layer with a treatment method including surface modification; forming a seed layer on the surface of the insulating resin layer by sputtering; and forming the wiring on the seed layer by electrolytic copper plating. The method may include, in this order, forming a surface treatment agent layer that covers a surface of the wiring by treating the surface of the wiring with a surface treatment agent for improving adhesion; and forming a modified region including pores in a surface layer of a first layer of the insulating resin layer by treating the surface of the first layer of the insulating resin layer with a treatment method including surface modification.

公开(公告)号：US20240306308A1

公开(公告)日：2024-09-12

申请号：US18650160

申请日：2024-04-30

Applicant: RESONAC CORPORATION

Inventor： Masaya TOBA ,  Kazuhiko KURAFUCHI ,  Takashi MASUKO ,  Kazuyuki MITSUKURA ,  Shinichiro ABE

IPC: H05K3/18 ,  C23C18/16 ,  C23C18/20 ,  C23C18/32 ,  C23C18/38 ,  H05K1/03

CPC classification number: H05K3/181 ,  C23C18/1605 ,  C23C18/165 ,  C23C18/20 ,  C23C18/32 ,  C23C18/38 ,  H05K1/032 ,  H05K2201/068

Abstract: A semiconductor package includes a wiring board and a semiconductor element mounted on the wiring board. The wiring board includes a first insulating material layer having a surface with an arithmetic average roughness Ra of 100 nm or less, a metal wiring provided on the surface of the first insulating material layer, and a second insulating material layer provided to cover the metal wiring. The metal wiring is configured by a metal layer in contact with the surface of the first insulating material layer and a conductive part stacked on a surface of the metal layer, and a nickel content rate of the metal layer is 0.25 to 20% by mass.

公开(公告)号：US20240015889A1

公开(公告)日：2024-01-11

申请号：US18044789

申请日：2021-09-09

Applicant: RESONAC CORPORATION

Inventor： Kei TOGASAKI ,  Kenichi IWASHITA ,  Keishi ONO ,  Mao NARITA ,  Kazuyuki MITSUKURA ,  Masaya TOBA

IPC: H05K1/18 ,  H05K3/12 ,  H05K3/18 ,  H05K3/02

CPC classification number: H05K1/181 ,  H05K3/1208 ,  H05K3/181 ,  H05K3/022

Abstract: A method for producing a wiring board, including: a step of pretreating the surface of a metal layer exposed into an opening by bringing the surface into contact with a pretreatment liquid at a predetermined pretreatment temperature; and a step of forming a copper plating layer on the metal layer by electrolytic plating. The resist layer and the pretreatment liquid are selected such that a mass change rate of the resist layer when the resist layer before being exposed and developed is immersed in the pretreatment liquid is −2.0% by mass or more. The mass change rate is a value calculated by Expression: Mass change rate (% by mass)={(W1−W0)/W0}×100. W1 is the mass of the resist layer after a laminated body including a resist layer 3 and a copper foil is immersed in the pretreatment liquid at the pretreatment temperature for 30 minutes.

公开(公告)号：US20230253215A1

公开(公告)日：2023-08-10

申请号：US18017954

申请日：2020-07-28

Applicant: Resonac Corporation

Inventor： Masaya TOBA ,  Kazuhiko KURAFUCHI ,  Takashi MASUKO ,  Kazuyuki MITSUKURA

IPC: H01L21/48 ,  H01L23/498 ,  C25D7/12 ,  C25D5/48 ,  C25D5/02 ,  C23C18/16 ,  C23C28/02

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  C25D7/123 ,  C25D5/48 ,  C25D5/022 ,  C23C18/1653 ,  C23C28/023 ,  C23C18/38

Abstract: A method for producing a wiring board according to the present disclosure includes: (A) forming a first insulating material layer on a supporting substrate; (B) forming a first opening part in the first insulating material layer; (C) forming a seed layer on the first insulating material layer; (D) providing a resist pattern on a surface of the seed layer; (E) forming a wiring part including a pad and wiring; (F) removing the resist pattern; (G) removing the seed layer; (H) applying a first surface treatment to the surface of the pad; (I) forming a second insulating material layer; (J) forming a second opening part in the second insulating material layer; (K) applying a second surface treatment to the surface of the pad; and (L) heating the second insulating material layer to a temperature equal to or higher than the glass transition temperature of the second insulating material layer.

公开(公告)号：US20240361697A1

公开(公告)日：2024-10-31

申请号：US18560234

申请日：2021-05-14

Applicant: Resonac Corporation

Inventor： Yuki IMAZU ,  Kazuyuki MITSUKURA ,  Masaya TOBA ,  Yu AOKI ,  Takuya KOMINE

IPC: G03F7/16 ,  G01N5/04 ,  G03F7/038 ,  G03F7/039 ,  H01L21/027

CPC classification number: G03F7/168 ,  G01N5/04 ,  G03F7/038 ,  G03F7/039 ,  H01L21/0274

Abstract: The present disclosure relates to a method for selecting a photosensitive resin composition, the method including: a step of applying a photosensitive resin composition on a substrate and drying the photosensitive resin composition to form a resin film; a step of heat-treating the resin film in a nitrogen atmosphere to obtain a cured film; and a step of raising the temperature from 25° C. to 300° C. at a rate of 10° C./min in a nitrogen atmosphere and then measuring weight loss of the cured film, in which a photosensitive resin composition capable of producing the cured film having a weight loss ratio at 300° C. of 1.0% to 6.0% is selected.

公开(公告)号：US20240057263A1

公开(公告)日：2024-02-15

申请号：US18260468

申请日：2021-01-06

Applicant: Resonac Corporation

Inventor： Masaya TOBA ,  Masaki YAMAGUCHI ,  Kazuyuki MITSUKURA

IPC: H05K3/18 ,  H05K3/10 ,  H05K3/02

CPC classification number: H05K3/181 ,  H05K3/107 ,  H05K3/025

Abstract: A method for manufacturing a wiring board including: providing a laminate including an insulating material layer and a copper layer provided on a surface of the insulating material layer, and in which the copper layer is an electroless copper plating layer; forming a resist pattern including a groove reaching a surface of the copper layer on the surface of the copper layer; and filling the groove with a conductive material containing copper by electrolytic copper plating. The thickness of the electroless copper plating layer is, for example, 20 nm to 200 nm.