公开(公告)号：US06580494B1

公开(公告)日：2003-06-17

申请号：US10198383

申请日：2002-07-16

申请人： Richard Ronald Hall ,  Robert Lee Lewis ,  How Tzu Lin ,  Peter M. Nichols ,  Robert David Sebesta

发明人： Richard Ronald Hall ,  Robert Lee Lewis ,  How Tzu Lin ,  Peter M. Nichols ,  Robert David Sebesta

IPC分类号： G03B2752

CPC分类号： G03F9/7003 ,  G03F7/70258 ,  G03F9/00

摘要： A photolithography imaging system and method that performs the tasks of mask alignment, panel recognition, establishing position offsets and adjusting mask rotation for accurate overlay imaging of the mask onto the panel, and correctly adjusting image magnification or reduction to properly size each stepped image to the panel distortion. This invention applies more directly to substrate panels whose dimensional stability is found difficult to control, repeatedly. More specifically, it applies to panels whose X axis distortion factor varies greatly from its Y axis distortion factor and the average adjustment of the image magnification or reduction does not satisfy tight registration requirements. What is new is that the calculation of the magnification or reduction adjustment is based on the mask image dimensions.

摘要翻译： 一种光刻成像系统和方法，其执行掩模对准，面板识别，建立位置偏移和调整掩模旋转的任务，以将掩模精确地叠加到面板上，并且正确地调整图像放大率或缩小以将每个步进图像适当地调整为 面板扭曲。 本发明更直接地应用于其尺寸稳定性难以控制的衬底面板。 更具体地说，它适用于其X轴失真因子从其Y轴失真因子变化很大的面板，并且图像放大或缩小的平均调整不满足严格的配准要求。 什么是新的是放大或缩小调整的计算是基于掩模图像尺寸。

公开(公告)号：US06580491B2

公开(公告)日：2003-06-17

申请号：US09749044

申请日：2000-12-26

申请人： Richard Ronald Hall ,  Robert Lee Lewis ,  How Tzu Lin ,  Peter Michael Nichols ,  Robert David Sebesta

发明人： Richard Ronald Hall ,  Robert Lee Lewis ,  How Tzu Lin ,  Peter Michael Nichols ,  Robert David Sebesta

IPC分类号： G03B2768

CPC分类号： G03F7/70466 ,  G03F7/70258 ,  G03F9/00 ,  H05K1/0269 ,  H05K3/0008 ,  H05K3/0082 ,  H05K2201/09918

摘要： Apparatus and method for compensating for distortion of the substrate of a printed circuit workpiece that involves performing two tasks. First, a mask that carries functional circuit features and alignment features is positioned rotatably so that the mask alignment features, when projected onto a table that holds the printed circuit workpiece, will be on a line extending parallel to one of two orthogonal axes of the table. Second, the spacing of alignment features on the printed circuit workpiece is determined and this determination is a measure of the distortion of the printed circuit workpiece substrate. A lens through which the mask image is projected is moved to adjust the magnification of the image in accordance with the measured distortion of the substrate of the printed circuit workpiece.

公开(公告)号：US5712192A

公开(公告)日：1998-01-27

申请号：US233193

申请日：1994-04-26

申请人： Robert Lee Lewis ,  Robert David Sebesta ,  Daniel Martin Waits

发明人： Robert Lee Lewis ,  Robert David Sebesta ,  Daniel Martin Waits

IPC分类号： H05K1/18 ,  H01L21/48 ,  H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H01L23/538 ,  H05K1/11 ,  H05K3/34 ,  H05K3/40 ,  H05K3/46 ,  H01L21/283 ,  H01L21/58

CPC分类号： H01L21/4846 ,  H01L23/49816 ,  H01L23/5385 ,  H05K1/112 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/1403 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K2201/09472 ,  H05K2201/10734 ,  H05K3/3431 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4644

摘要： A process for manufacturing circuitized substrate for use in an electronic package wherein the substrate, e.g., ceramic, includes more than one conductive layer, e.g., copper, thereon separated by a suitable dielectric material, e.g., polyimide. Each layer includes its own conductive location(s) which are designed for being directly electrically connected, e.g., using solder, to respective contact sites on a semiconductor chip positioned on the substrate to form part of the final package. A method for making such a package is also provided. Significantly, the resulting package does not include interconnections between the conductive layers at the desired contact locations, these locations, as mentioned, instead being directly connected to the chip.

摘要翻译： 一种制造用于电子封装的电路化衬底的方法，其中衬底例如陶瓷包括多于一个的导电层，例如铜，其上由合适的电介质材料例如聚酰亚胺分隔开。 每个层包括其自身的导电位置，其被设计用于直接电连接（例如使用焊料）到位于衬底上的半导体芯片上的相应接触位置，以形成最终封装的一部分。 还提供了制造这种包装的方法。 显着地，所得到的封装不包括在所需接触位置处的导电层之间的互连，如上所述，这些位置而不是直接连接到芯片。

公开(公告)号：US06429113B1

公开(公告)日：2002-08-06

申请号：US09518447

申请日：2000-03-03

申请人： Robert Lee Lewis ,  Robert David Sebesta ,  Daniel Martin Waits

发明人： Robert Lee Lewis ,  Robert David Sebesta ,  Daniel Martin Waits

IPC分类号： H01L2144

CPC分类号： H05K1/112 ,  H01L21/4846 ,  H01L23/49816 ,  H01L23/5385 ,  H01L2924/0002 ,  H05K3/3436 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/10734 ,  H01L2924/00

摘要： A method of making a circuitized substrate for use in an electronic package wherein the substrate, e.g., ceramic, includes more than one conductive layer, e.g., copper, thereon separated by a suitable dielectric material, e.g., polyimide. Each layer includes its own conductive location(s) which are designed for being directly electrically connected, e.g. using solder, to respective contact sites on a semiconductor chip to form part of the final package. Significantly, the resulting package does not include interconnections between the conductive layers at the desired contact locations; these locations, as mentioned, instead being directly connected to the chip.

摘要翻译： 制造用于电子封装的电路化衬底的方法，其中衬底例如陶瓷包括多于一个的导电层，例如铜，其上由合适的电介质材料（例如聚酰亚胺）分隔开。 每个层包括其自己的导电位置，其被设计用于直接电连接，例如， 使用焊料到半导体芯片上的相应接触部位以形成最终封装的一部分。 显着地，所得到的封装不包括在期望的接触位置处的导电层之间的互连; 这些位置，如上所述，而是直接连接到芯片。

公开(公告)号：US5858254A

公开(公告)日：1999-01-12

申请号：US789813

申请日：1997-01-28

申请人： Peter Lynn Balzer ,  Robert Lee Lewis ,  Robert David Sebesta

发明人： Peter Lynn Balzer ,  Robert Lee Lewis ,  Robert David Sebesta

IPC分类号： H01L23/538 ,  H05K1/11 ,  H05K3/46 ,  C23F1/00

CPC分类号： H01L23/5384 ,  H05K1/112 ,  H05K3/467 ,  H01L2924/0002 ,  H05K2201/09472 ,  H05K2201/10674

摘要： A multilayer circuit fabrication approach and circuitized substrate are presented wherein at least two conductive layers are formed over a substrate. The conductive layers are separated by a first dielectric layer and the structure is encapsulated with a second dielectric layer. The first dielectric layer includes open areas exposing a portion of the underlying support structure aligned to those areas where contact points are to reside in the second conductive layer. The first dielectric layer comprises a blanket dielectric layer such that recesses are defined in the upper surface thereof aligned to the open areas of the first conductive layer. The second conductive layer thus resides in two planes, both of which comprise planes other than a plane of the first conductive layer. A plurality of openings can be simultaneously formed to expose contact points in both the first and second conductive layers.

摘要翻译： 提出了一种多层电路制造方法和电路化衬底，其中在衬底上形成至少两个导电层。 导电层由第一介电层分开，并且结构被第二介电层封装。 第一电介质层包括暴露下面的支撑结构的一部分的开放区域，其与接触点将驻留在第二导电层中的那些区域对准。 第一电介质层包括覆盖电介质层，使得在其上表面中限定了与第一导电层的开放区域对准的凹部。 因此，第二导电层位于两个平面中，它们都包括除了第一导电层的平面之外的平面。 可以同时形成多个开口以暴露第一和第二导电层中的接触点。

公开(公告)号：US06569604B1

公开(公告)日：2003-05-27

申请号：US09345723

申请日：1999-06-30

申请人： Anilkumar Chinuprasad Bhatt ,  Francis Joseph Downes, Jr. ,  Robert Lee Lewis ,  Voya R. Markovich

发明人： Anilkumar Chinuprasad Bhatt ,  Francis Joseph Downes, Jr. ,  Robert Lee Lewis ,  Voya R. Markovich

IPC分类号： G03C500

CPC分类号： H01L23/49816 ,  H01L23/49827 ,  H01L2224/16 ,  H05K3/0023 ,  H05K3/0035 ,  H05K3/4602 ,  H05K2201/09827 ,  H05K2203/1476

摘要： A blind via structure, and associated laser ablation methods of formation, that includes a blind via within a photoimageable dielectric (PID) layer on a substrate, such that the sidewall of the blind via makes an obtuse angle with the blind end of the blind via. The obtuse-angled sidewall may be formed by executing two processes in sequence. In the first process, photoimaging of the PID layer, with selective exposure to ultraviolet light, results in one or more blind vias having acute-angled sidewalls. The photoimaging cross links the PID material that had been selectively exposed to ultraviolet light such that a subsequent developing step removes PID material not cross linked, or weakly cross linked, to simultaneously form multiple blind vias having different sized openings. In the second process, laser ablation is selectively employed to remove the acute-angled sidewalls from particular blind vias in a way that forms replacement obtuse-angled sidewalls in the laser-ablated blind vias. Alternatively, the first process involving photoimaging may be omitted such that the second step involving laser ablation forms the entire obtuse-angled blind via. The resultant blind via structure includes at least one blind via having an obtuse-angled sidewall, and optionally, at least one blind via having an acute-angled sidewall.

摘要翻译： 盲通孔结构和相关联的激光烧蚀消融方法，其包括在衬底上的可光成像电介质（PID）层内的盲通孔，使得盲通孔的侧壁与盲孔的盲端通过钝角 。 可以通过依次执行两个过程来形成钝角侧壁。 在第一个过程中，通过选择性地暴露在紫外线下的PID层的光成像产生一个或多个具有锐角侧壁的盲孔。 光学成像将选择性暴露于紫外线的PID材料交叉连接，使得随后的显影步骤除去未交联或弱交联的PID材料，以同时形成具有不同尺寸开口的多个盲孔。 在第二过程中，激光烧蚀被选择性地用于在激光烧蚀的盲孔中形成置换钝角侧壁的方式从特定的盲孔中去除锐角侧壁。 或者，可以省略涉及光成像的第一过程，使得涉及激光烧蚀的第二步骤形成整个钝角盲孔。 所得到的盲通孔结构包括至少一个具有钝角侧壁的盲孔，并且可选地，至少一个具有锐角侧壁的盲孔。