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公开(公告)号：US5858254A
公开(公告)日：1999-01-12
申请号：US789813
申请日：1997-01-28
IPC分类号： H01L23/538 , H05K1/11 , H05K3/46 , C23F1/00
CPC分类号： H01L23/5384 , H05K1/112 , H05K3/467 , H01L2924/0002 , H05K2201/09472 , H05K2201/10674
摘要： A multilayer circuit fabrication approach and circuitized substrate are presented wherein at least two conductive layers are formed over a substrate. The conductive layers are separated by a first dielectric layer and the structure is encapsulated with a second dielectric layer. The first dielectric layer includes open areas exposing a portion of the underlying support structure aligned to those areas where contact points are to reside in the second conductive layer. The first dielectric layer comprises a blanket dielectric layer such that recesses are defined in the upper surface thereof aligned to the open areas of the first conductive layer. The second conductive layer thus resides in two planes, both of which comprise planes other than a plane of the first conductive layer. A plurality of openings can be simultaneously formed to expose contact points in both the first and second conductive layers.
摘要翻译： 提出了一种多层电路制造方法和电路化衬底，其中在衬底上形成至少两个导电层。 导电层由第一介电层分开，并且结构被第二介电层封装。 第一电介质层包括暴露下面的支撑结构的一部分的开放区域，其与接触点将驻留在第二导电层中的那些区域对准。 第一电介质层包括覆盖电介质层，使得在其上表面中限定了与第一导电层的开放区域对准的凹部。 因此，第二导电层位于两个平面中，它们都包括除了第一导电层的平面之外的平面。 可以同时形成多个开口以暴露第一和第二导电层中的接触点。
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公开(公告)号：US06429113B1
公开(公告)日：2002-08-06
申请号：US09518447
申请日：2000-03-03
IPC分类号： H01L2144
CPC分类号： H05K1/112 , H01L21/4846 , H01L23/49816 , H01L23/5385 , H01L2924/0002 , H05K3/3436 , H05K3/4644 , H05K2201/09472 , H05K2201/10734 , H01L2924/00
摘要： A method of making a circuitized substrate for use in an electronic package wherein the substrate, e.g., ceramic, includes more than one conductive layer, e.g., copper, thereon separated by a suitable dielectric material, e.g., polyimide. Each layer includes its own conductive location(s) which are designed for being directly electrically connected, e.g. using solder, to respective contact sites on a semiconductor chip to form part of the final package. Significantly, the resulting package does not include interconnections between the conductive layers at the desired contact locations; these locations, as mentioned, instead being directly connected to the chip.
摘要翻译： 制造用于电子封装的电路化衬底的方法，其中衬底例如陶瓷包括多于一个的导电层，例如铜，其上由合适的电介质材料（例如聚酰亚胺）分隔开。 每个层包括其自己的导电位置，其被设计用于直接电连接，例如， 使用焊料到半导体芯片上的相应接触部位以形成最终封装的一部分。 显着地，所得到的封装不包括在期望的接触位置处的导电层之间的互连; 这些位置，如上所述，而是直接连接到芯片。
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3.发明授权Method and system of distortion compensation in a projection imaging expose system 有权投影成像曝光系统中失真补偿的方法和系统公开(公告)号：US06580494B1
公开(公告)日：2003-06-17
申请号：US10198383
申请日：2002-07-16
IPC分类号： G03B2752
CPC分类号： G03F9/7003 , G03F7/70258 , G03F9/00
摘要： A photolithography imaging system and method that performs the tasks of mask alignment, panel recognition, establishing position offsets and adjusting mask rotation for accurate overlay imaging of the mask onto the panel, and correctly adjusting image magnification or reduction to properly size each stepped image to the panel distortion. This invention applies more directly to substrate panels whose dimensional stability is found difficult to control, repeatedly. More specifically, it applies to panels whose X axis distortion factor varies greatly from its Y axis distortion factor and the average adjustment of the image magnification or reduction does not satisfy tight registration requirements. What is new is that the calculation of the magnification or reduction adjustment is based on the mask image dimensions.
摘要翻译： 一种光刻成像系统和方法，其执行掩模对准，面板识别，建立位置偏移和调整掩模旋转的任务，以将掩模精确地叠加到面板上，并且正确地调整图像放大率或缩小以将每个步进图像适当地调整为 面板扭曲。 本发明更直接地应用于其尺寸稳定性难以控制的衬底面板。 更具体地说，它适用于其X轴失真因子从其Y轴失真因子变化很大的面板，并且图像放大或缩小的平均调整不满足严格的配准要求。 什么是新的是放大或缩小调整的计算是基于掩模图像尺寸。
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公开(公告)号：US5712192A
公开(公告)日：1998-01-27
申请号：US233193
申请日：1994-04-26
IPC分类号： H05K1/18 , H01L21/48 , H01L21/60 , H01L23/12 , H01L23/498 , H01L23/538 , H05K1/11 , H05K3/34 , H05K3/40 , H05K3/46 , H01L21/283 , H01L21/58
CPC分类号： H01L21/4846 , H01L23/49816 , H01L23/5385 , H05K1/112 , H01L2224/0401 , H01L2224/05571 , H01L2224/1403 , H01L2924/0002 , H01L2924/09701 , H05K2201/09472 , H05K2201/10734 , H05K3/3431 , H05K3/3436 , H05K3/4007 , H05K3/4644
摘要： A process for manufacturing circuitized substrate for use in an electronic package wherein the substrate, e.g., ceramic, includes more than one conductive layer, e.g., copper, thereon separated by a suitable dielectric material, e.g., polyimide. Each layer includes its own conductive location(s) which are designed for being directly electrically connected, e.g., using solder, to respective contact sites on a semiconductor chip positioned on the substrate to form part of the final package. A method for making such a package is also provided. Significantly, the resulting package does not include interconnections between the conductive layers at the desired contact locations, these locations, as mentioned, instead being directly connected to the chip.
摘要翻译： 一种制造用于电子封装的电路化衬底的方法，其中衬底例如陶瓷包括多于一个的导电层，例如铜，其上由合适的电介质材料例如聚酰亚胺分隔开。 每个层包括其自身的导电位置，其被设计用于直接电连接（例如使用焊料）到位于衬底上的半导体芯片上的相应接触位置，以形成最终封装的一部分。 还提供了制造这种包装的方法。 显着地，所得到的封装不包括在所需接触位置处的导电层之间的互连，如上所述，这些位置而不是直接连接到芯片。
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5.发明授权公开(公告)号：US06580491B2
公开(公告)日：2003-06-17
申请号：US09749044
申请日：2000-12-26
申请人： Richard Ronald Hall , Robert Lee Lewis , How Tzu Lin , Peter Michael Nichols , Robert David Sebesta
发明人： Richard Ronald Hall , Robert Lee Lewis , How Tzu Lin , Peter Michael Nichols , Robert David Sebesta
IPC分类号： G03B2768
CPC分类号： G03F7/70466 , G03F7/70258 , G03F9/00 , H05K1/0269 , H05K3/0008 , H05K3/0082 , H05K2201/09918
摘要： Apparatus and method for compensating for distortion of the substrate of a printed circuit workpiece that involves performing two tasks. First, a mask that carries functional circuit features and alignment features is positioned rotatably so that the mask alignment features, when projected onto a table that holds the printed circuit workpiece, will be on a line extending parallel to one of two orthogonal axes of the table. Second, the spacing of alignment features on the printed circuit workpiece is determined and this determination is a measure of the distortion of the printed circuit workpiece substrate. A lens through which the mask image is projected is moved to adjust the magnification of the image in accordance with the measured distortion of the substrate of the printed circuit workpiece.
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公开(公告)号：US06989297B2
公开(公告)日：2006-01-24
申请号：US10926210
申请日：2004-08-25
CPC分类号： H05K1/0265 , H01L23/498 , H01L23/49816 , H01L23/49822 , H01L24/45 , H01L24/48 , H01L2224/16 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H05K3/243 , H05K3/427 , H05K2201/0352 , H05K2201/09736 , H05K2201/10674 , H05K2203/049 , H01L2924/00014 , H01L2924/00015
摘要： An electronic structure, and associated method of fabrication, that includes a substrate having attached circuit elements and conductive bonding pads of varying thickness. Pad categories relating to pad thickness include thick pads (17 to 50 microns), medium pads (10–17 microns), and thin pads (3 to 10 microns). A thick pad is used for coupling a ball grid array (BGA) to a substrate with attachment of the BGA to a circuit card. A medium pad is useful in flip-chip bonding of a chip to a substrate by use of an interfacing small solder ball. A thin copper pad, coated with a nickel-gold layer, is useful for coupling a chip to a substrate by use of a wirebond interface. The electrical structure includes an electrical coupling of two pads having different thickness, such that the pads are located either on the same surface of a substrate or on-opposite sides of a substrate.
摘要翻译： 一种电子结构和相关的制造方法，其包括具有附接的电路元件的衬底和不同厚度的导电接合焊盘。 与垫厚相关的垫类别包括厚垫（17至50微米），中垫（10-17微米）和薄垫（3至10微米）。 使用厚焊盘将球栅阵列（BGA）耦合到具有BGA与电路卡的附接的基板。 介质垫可用于通过使用接口小的焊球将芯片倒装芯片连接到基板。 涂覆有镍 - 金层的薄铜焊盘可用于通过引线接口将芯片耦合到衬底。 电结构包括具有不同厚度的两个焊盘的电耦合，使得焊盘位于衬底的相同表面或衬底的相对侧上。
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公开(公告)号：US06815709B2
公开(公告)日：2004-11-09
申请号：US09863978
申请日：2001-05-23
IPC分类号： H01L3524
CPC分类号： C25D7/123 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H05K3/205 , Y10T428/12361 , Y10T428/12438 , Y10T428/12569 , H01L2924/00014
摘要： Embedded flush circuitry features are provided by providing a carrier foil having an electrically conductive layer therein and coating the electrically conductive layer with a dielectric material. Circuitry features are formed in the dielectric material and conductive metal is plated to fill the circuitry features.
摘要翻译： 通过提供其中具有导电层的载体箔并且用电介质材料涂覆导电层来提供嵌入式嵌入式电路特征。 在电介质材料中形成电路特征，并且电镀导电金属以填充电路特征。
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公开(公告)号：US06900545B1
公开(公告)日：2005-05-31
申请号：US09526957
申请日：2000-03-16
CPC分类号： H05K1/0265 , H01L23/498 , H01L23/49816 , H01L23/49822 , H01L24/45 , H01L24/48 , H01L2224/16 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H05K3/243 , H05K3/427 , H05K2201/0352 , H05K2201/09736 , H05K2201/10674 , H05K2203/049 , H01L2924/00014 , H01L2924/00015
摘要： An electronic structure, and associated method of fabrication, that includes a substrate having attached circuit elements and conductive bonding pads of varying thickness. Pad categories relating to pad thickness include thick pads (17 to 50 microns), medium pads (10-17 microns), and thin pads (3 to 10 microns). A thick pad is used for coupling a ball grid array (BGA) to a substrate with attachment of the BGA to a circuit card. A medium pad is useful in flip-chip bonding of a chip to a substrate by use of an interfacing small solder ball. A thin copper pad, coated with a nickel-gold layer, is useful for coupling a chip to a substrate by use of a wirebond interface. The electrical structure includes an electrical coupling of two pads having different thickness, such that the pads are located either on the same surface of a substrate or on opposite sides of a substrate.
摘要翻译： 一种电子结构和相关的制造方法，其包括具有附接的电路元件的衬底和不同厚度的导电接合焊盘。 与垫厚相关的垫类别包括厚垫（17至50微米），中垫（10-17微米）和薄垫（3至10微米）。 使用厚焊盘将球栅阵列（BGA）耦合到具有BGA与电路卡的附接的基板。 介质垫可用于通过使用接口小的焊球将芯片倒装芯片连接到基板。 涂覆有镍 - 金层的薄铜焊盘可用于通过引线接口将芯片耦合到衬底。 电结构包括具有不同厚度的两个焊盘的电耦合，使得焊盘位于衬底的相同表面上或者位于衬底的相对侧上。
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9.发明授权
公开(公告)号：US6013417A
公开(公告)日：2000-01-11
申请号：US54374
申请日：1998-04-02
CPC分类号： H05K3/064 , G03F7/0035 , H05K3/0094 , H05K2203/0588 , H05K2203/068 , H05K2203/1394 , H05K2203/1572 , H05K3/427
摘要： Circuitry is formed on a substrate having at least one plated through-hole employing two different photoresist materials. A first photoresist is applied on a conductive layer located on a substrate and is developed to define a desired conductive circuit pattern. A second photoresist is laminated onto the structure and is developed so that the second photoresist material remains in the vicinity of the through-hole. The conductive layer is etched to provide the desired circuit pattern, and the remaining portions of the second and first photoresists are removed.
摘要翻译： 在具有至少一个使用两种不同光致抗蚀剂材料的电镀通孔的基板上形成电路。 将第一光致抗蚀剂施加在位于衬底上的导电层上，并显影以限定所需的导电电路图案。 将第二光致抗蚀剂层压到结构上并显影，使得第二光致抗蚀剂材料保留在通孔附近。 蚀刻导电层以提供期望的电路图案，并且去除第二和第一光致抗蚀剂的剩余部分。
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公开(公告)号：US07098136B2
公开(公告)日：2006-08-29
申请号：US10921839
申请日：2004-08-20
IPC分类号： H01L21/302 , B44C1/22 , H05K1/09
CPC分类号： C25D7/123 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H05K3/205 , Y10T428/12361 , Y10T428/12438 , Y10T428/12569 , H01L2924/00014
摘要： Embedded flush circuitry features are provided by providing a carrier foil having an electrically conductive layer therein and coating the electrically conductive layer with a dielectric material. Circuitry features are formed in the dielectric material and conductive metal is plated to fill the circuitry features.
摘要翻译： 通过提供其中具有导电层的载体箔并且用电介质材料涂覆导电层来提供嵌入式嵌入式电路特征。 在电介质材料中形成电路特征，并且电镀导电金属以填充电路特征。
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