公开(公告)号：US07700485B2

公开(公告)日：2010-04-20

申请号：US11872227

申请日：2007-10-15

申请人： Rita J. Klein

发明人： Rita J. Klein

IPC分类号： H01L21/00

CPC分类号： G11C13/0011 ,  C23C18/165 ,  C23C18/1837 ,  C25D7/123 ,  G11C13/0004 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143 ,  H01L45/1658 ,  Y10T428/31678

摘要： Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a conductive material over the chalcogenide material, diffusing metal from the diffusion layer into the chalcogenide material resulting in a metal-comprising resistance variable material, and then plating a conductive material to a desired thickness to form a second (upper) electrode. In another embodiment, the surface of the chalcogenide layer can be treated with an activating agent such as palladium, a conductive metal can be electrolessly plated onto the activated areas to form a thin diffusion layer, metal ions from the diffusion layer can be diffused into the chalogenide material to form a resistance variable material, and a conductive material plated over the resistance variable material to form the upper electrode. The invention provides a process for controlling the diffusion of metal into the chalcogenide material to form a resistance variable material by depositing the mass of the upper electrode by a metal plating technique.

摘要翻译： 提供了非易失性，电阻可变存储器件，集成电路元件以及形成这种器件的方法。 根据本发明的方法的一个实施例，存储器件可以通过在第一（下）电极上沉积硫族化物材料，在硫族化物材料上溅射沉积导电材料的薄扩散层，从扩散中扩散金属来制造 形成硫族化物材料，得到含金属的电阻变化材料，然后将导电材料镀覆到所需厚度以形成第二（上）电极。 在另一个实施方案中，硫族化物层的表面可以用诸如钯的活化剂处理，导电金属可以无电镀在活化区上形成薄的扩散层，来自扩散层的金属离子可以扩散到 硫族化物材料以形成电阻可变材料，以及镀在电阻可变材料上以形成上电极的导电材料。 本发明提供一种通过金属电镀技术沉积上部电极的质量来控制金属向硫族化物材料的扩散以形成电阻可变材料的方法。

公开(公告)号：US07686874B2

公开(公告)日：2010-03-30

申请号：US11168675

申请日：2005-06-28

申请人： Rita J. Klein ,  Adam J. Regner, III

发明人： Rita J. Klein ,  Adam J. Regner, III

IPC分类号： C23C18/34

CPC分类号： C23C18/1608 ,  C23C18/34

摘要： An electroless plating composition comprising succinic acid, potassium carbonate, a source of cobalt metal ions, a reducing agent, and water is provided. An optional buffering agent may also be included in the composition. The composition may be used to deposit cobalt metal in or on semiconductor substrate surfaces including vias, trenches, and interconnects.

摘要翻译： 提供了包含琥珀酸，碳酸钾，钴金属离子源，还原剂和水的化学镀组合物。 组合物中也可以包括任选的缓冲剂。 组合物可用于在包括通孔，沟槽和互连的半导体衬底表面中或其上沉积钴金属。

公开(公告)号：US07666776B2

公开(公告)日：2010-02-23

申请号：US11218232

申请日：2005-09-01

申请人： Dale W. Collins ,  Rita J. Klein ,  James E. Green

发明人： Dale W. Collins ,  Rita J. Klein ,  James E. Green

IPC分类号： H01L21/44

CPC分类号： H01L21/76885 ,  H01L21/76834 ,  H01L21/76852

摘要： The invention includes methods of forming pluralities of electrically conductive structures. The methods can include formation of a gradient-containing material across a substrate and in direct physical contact with conductive surfaces of nodes. The gradient-containing material can consist essentially of tantalum nitride at a lowermost portion in contact with the conductive surfaces, consist essentially of tantalum at an uppermost portion, and have a TaN/Ta gradient extending between the lowermost and uppermost portions. Alternatively, the gradient-containing material can have a Co/W gradient extending therethrough. Conductive structures can be formed over the gradient-containing material. The invention also includes constructions comprising electrically conductive lines over a material having a TaN/Ta gradient, or a W/Co gradient, extending therethrough.

摘要翻译： 本发明包括形成多个导电结构的方法。 这些方法可以包括在衬底上形成含梯度的材料，并且与节点的导电表面直接物理接触。 含梯度的材料可以基本上由在与导电表面接触的最下部分的氮化钽组成，其基本上由最上部的钽构成，并且具有在最下部和最上部之间延伸的TaN / Ta梯度。 或者，含梯度的材料可以具有从其延伸的Co / W梯度。 可以在含梯度材料上形成导电结构。 本发明还包括在TaN / Ta梯度或延伸穿过其中的W / Co梯度的材料上包括导电线的构造。

公开(公告)号：US07344977B2

公开(公告)日：2008-03-18

申请号：US11053794

申请日：2005-02-08

申请人： Dale W. Collins ,  Richard H. Lane ,  Rita J. Klein

发明人： Dale W. Collins ,  Richard H. Lane ,  Rita J. Klein

IPC分类号： H01L21/4763

CPC分类号： H01L27/10852 ,  H01L21/2885 ,  H01L27/10808 ,  H01L27/10817 ,  H01L28/60 ,  H01L28/90 ,  Y10S257/906

摘要： The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.

摘要翻译： 本发明包括电化学处理半导体衬底的方法。 本发明包括电镀物质的方法。 提供了具有限定的第一和第二区域的基板。 第一和第二区域可以由单个掩模限定，因此可以被认为是相对于彼此自对准的。 在第一区域上形成第一导电材料，并且在第二区域上形成第二导电材料。 第一和第二导电材料暴露于电解溶液，同时向第一和第二导电材料提供电流。 在将第一和第二导电材料暴露于电解液期间，期望的物质选择性地电镀到第一导电材料上。 本发明还包括形成电容器结构的方法。

公开(公告)号：US06884723B2

公开(公告)日：2005-04-26

申请号：US10028040

申请日：2001-12-21

申请人： Nishant Sinha ,  Rita J. Klein

发明人： Nishant Sinha ,  Rita J. Klein

IPC分类号： B24B37/00 ,  C09K3/14 ,  C23F3/00 ,  H01L21/304 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/3212 ,  C09G1/02 ,  C23F3/06

摘要： A planarization method includes providing a second and/or third row Group VIII metal-containing surface (preferably, a platinum-containing surface) and positioning it for contact with a polishing surface in the presence of a planarization composition that includes a complexing agent.

公开(公告)号：US07179716B2

公开(公告)日：2007-02-20

申请号：US11054130

申请日：2005-02-08

申请人： Dale W. Collins ,  Richard H. Lane ,  Rita J. Klein

发明人： Dale W. Collins ,  Richard H. Lane ,  Rita J. Klein

IPC分类号： H01L21/76

CPC分类号： H01L27/10852 ,  H01L21/2885 ,  H01L27/10808 ,  H01L27/10817 ,  H01L28/60 ,  H01L28/90 ,  Y10S257/906

摘要： The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.

摘要翻译： 本发明包括电化学处理半导体衬底的方法。 本发明包括电镀物质的方法。 提供了具有限定的第一和第二区域的基板。 第一和第二区域可以由单个掩模限定，因此可以被认为是相对于彼此自对准的。 在第一区域上形成第一导电材料，并且在第二区域上形成第二导电材料。 第一和第二导电材料暴露于电解溶液，同时向第一和第二导电材料提供电流。 在将第一和第二导电材料暴露于电解液期间，期望的物质选择性地电镀到第一导电材料上。 本发明还包括形成电容器结构的方法。

公开(公告)号：US06511576B2

公开(公告)日：2003-01-28

申请号：US09929296

申请日：2001-08-13

申请人： Rita J. Klein

发明人： Rita J. Klein

IPC分类号： H01L2100

CPC分类号： H01L28/40 ,  B24B37/042 ,  H01L21/3212 ,  H01L28/60

摘要： A method for planarizing a microelectronic substrate. In one embodiment, the microelectronic substrate includes an insulating portion having at least one aperture that is empty or at least partially filled with a sacrificial material. The method can include pressing a planarizing medium having small abrasive elements against the microelectronic substrate and moving at least one of the microelectronic substrate and the planarizing medium relative to the other to remove material from the microelectronic substrate. In one aspect of the invention, the abrasive elements can include flumed silica particles having a mean cross-sectional dimension of less than about 200 nanometers and/or colloidal particles having a mean cross-sectional dimension of less than about fifty nanometers. The smaller abrasive elements can reduce formation of cracks or other defects in the insulating material during planarization to improve the reliability and performance of the microelectronic device.

摘要翻译： 一种用于平面化微电子衬底的方法。 在一个实施例中，微电子衬底包括绝缘部分，其具有至少一个空洞或至少部分地填充有牺牲材料的孔。 该方法可以包括将具有小研磨元件的平坦化介质压靠在微电子衬底上，并且相对于另一个移动微电子衬底和平坦化介质中的至少一个以从微电子衬底去除材料。 在本发明的一个方面，研磨元件可以包括具有小于约200纳米的平均横截面尺寸的蒸发二氧化硅颗粒和/或平均横截面尺寸小于约五十纳米的胶体颗粒。 在平坦化期间，较小的研磨元件可以减少绝缘材料中的裂纹或其它缺陷的形成，以提高微电子器件的可靠性和性能。

公开(公告)号：US06306768B1

公开(公告)日：2001-10-23

申请号：US09441923

申请日：1999-11-17

申请人： Rita J. Klein

发明人： Rita J. Klein

IPC分类号： H01L2100

CPC分类号： H01L28/40 ,  B24B37/042 ,  H01L21/3212 ,  H01L28/60

摘要： A method for planarizing a microelectronic substrate. In one embodiment, the microelectronic substrate includes an insulating portion having at least one aperture that is empty or at least partially filled with a sacrificial material. The method can include pressing a planarizing medium having small abrasive elements against the microelectronic substrate and moving at least one of the microelectronic substrate and the planarizing medium relative to the other to remove material from the microelectronic substrate. In one aspect of the invention, the abrasive elements can include fumed silica particles having a mean cross-sectional dimension of less than about 200 nanometers and/or colloidal particles having a mean cross-sectional dimension of less than about fifty nanometers. The smaller abrasive elements can reduce the formation of cracks or other defects in the insulating material during planarization to improve the reliability and performance of the microelectronic device.

摘要翻译： 一种用于平面化微电子衬底的方法。 在一个实施例中，微电子衬底包括绝缘部分，其具有至少一个空洞或至少部分地填充有牺牲材料的孔。 该方法可以包括将具有小研磨元件的平坦化介质压靠在微电子衬底上，并且相对于另一个移动微电子衬底和平坦化介质中的至少一个以从微电子衬底去除材料。 在本发明的一个方面，研磨元件可以包括平均横截面尺寸小于约200纳米的热解二氧化硅颗粒和/或平均横截面尺寸小于约五十纳米的胶体颗粒。 较小的研磨元件可以在平坦化期间减少绝缘材料中的裂纹或其它缺陷的形成，以提高微电子器件的可靠性和性能。

公开(公告)号：US20190067028A1

公开(公告)日：2019-02-28

申请号：US15686526

申请日：2017-08-25

申请人： Andrew L. Li ,  Prashant Raghu ,  Sanjeev Sapra ,  Rita J. Klein ,  Sanh D. Tang ,  Sourabh Dhir

发明人： Andrew L. Li ,  Prashant Raghu ,  Sanjeev Sapra ,  Rita J. Klein ,  Sanh D. Tang ,  Sourabh Dhir

IPC分类号： H01L21/311 ,  H01L21/02 ,  H01L27/108 ,  H01L21/66 ,  H01L21/67

摘要： Various embodiments comprise methods of selectively etching oxides over nitrides in a vapor-etch cyclic process. In one embodiment, the method includes, in a first portion of the vapor-etch cyclic process, exposing a substrate having oxide features and nitride features formed thereon to selected etchants in a vapor-phase chamber; transferring the substrate to a post-etch heat treatment chamber; and heating the substrate to remove etchant reaction products from the substrate. In a second portion of the vapor-etch cyclic process, the method continues with transferring the substrate from the post-etch heat treatment chamber to the vapor-phase chamber; exposing the substrate to the selected etchants in the vapor-phase chamber; transferring the substrate to the post-etch heat treatment chamber; and heating the substrate to remove additional etchant reaction products from the substrate. Apparatuses for performing the method and additional methods are also disclosed.

公开(公告)号：US08603318B2

公开(公告)日：2013-12-10

申请号：US13098572

申请日：2011-05-02

申请人： Rita J. Klein ,  Dale W. Collins ,  Paul Morgan ,  Joseph N. Greeley ,  Nishant Sinha

发明人： Rita J. Klein ,  Dale W. Collins ,  Paul Morgan ,  Joseph N. Greeley ,  Nishant Sinha

IPC分类号： C25F3/16

CPC分类号： H01L21/67086 ,  B82Y30/00 ,  C23F1/02 ,  C23F1/10 ,  H01B1/122 ,  H01L21/32115 ,  H01L21/67075

摘要： An electrolyte solution, methods, and systems for selectively removing a conductive metal from a substrate are provided. The electrolyte solution comprising nanoparticles that are more noble than the conductive metal being removed, is applied to a substrate to remove the conductive metal selectively relative to a dielectric material without application of an external potential or contact of a processing pad with a surface of the substrate. The solutions and methods can be applied, for example, to remove a conductive metal layer (e.g., barrier metal) selectively relative to a dielectric material and to a materially different conductive metal (e.g., copper interconnect) without application of an external potential or contact of a processing pad with the surface of the substrate.

摘要翻译： 提供了一种用于从衬底选择性地去除导电金属的电解质溶液，方法和系统。 将包含比被除去的导电金属更高的纳米颗粒的电解质溶液施加到基底上以相对于介电材料选择性地去除导电金属，而不施加外部电位或处理垫与基底的表面的接触 。 解决方案和方法可以应用于例如相对于电介质材料选择性去除导电金属层（例如，阻挡金属），并且可以应用于物理上不同的导电金属（例如，铜互连）而不施加外部电位或接触 具有衬底表面的处理衬垫。