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1.发明授权Method of proton-enhanced diffusion for simultaneously forming integrated circuit regions of varying depths 失效用于同时形成不同深度的集成电路区域的质子增强扩散方法
公开(公告)号：US3982967A
公开(公告)日：1976-09-28
申请号：US562370
申请日：1975-03-26
IPC分类号： C30B31/22 , H01L21/22 , H01L21/265 , H01L21/761 , H01L21/263
CPC分类号： H01L21/263 , H01L21/26506
摘要： In integrated circuit fabrication, a method is provided for simultaneously forming two regions of the same conductivity-type such as the base and isolation regions. In one embodiment, an epitaxial layer of one conductivity-type is formed on a substrate of opposite conductivity-type, after which dopant ions of the opposite conductivity-type are introduced into the epitaxial surface areas which are to provide the base and isolation regions, and in addition, the isolation regions are bombarded with non-dopant ions having a maximum atomic number of two, e.g., hydrogen or helium ion while the base regions are appropriately masked and remain umbombarded, said bombardment is carried out at temperatures below 300.degree. C, preferably room temperature. The bombardment is preferably carried out so that the non-dopant ions are implanted primarily in regions below the isolation regions. Next, the wafer is heated at a temperature at a range of from 600.degree. - 900.degree. C which is substantially below normal drive-in diffusion temperatures for unbombarded doped regions. The heating to be maintained for a period sufficient to drive-in diffuse the bombarded isolation regions through the epitaxial layer into contact with the substrate but is insufficient to drive-in the unbombarded base regions to such a depth.
摘要翻译： 在集成电路制造中，提供了一种用于同时形成相同导电类型的两个区域的方法，例如基极和隔离区域。 在一个实施例中，在相反导电型的衬底上形成一种导电类型的外延层，之后将相反导电类型的掺杂剂离子引入到要提供基极和隔离区域的外延表面区域中， 此外，隔离区域用最大原子数为2的非掺杂离子（例如氢或氦离子）进行轰击，同时基底区域被适当地掩蔽并且保持不变，所述轰击在低于300℃的温度下进行 ，优选室温。 优选进行轰击，使得非掺杂剂离子主要被注入在隔离区域下方的区域中。 接下来，将晶片在600-900℃的温度范围内加热，这对于未掺杂的掺杂区域基本上低于正常的驱动扩散温度。 保持加热持续足以驱动的时间段将被轰击的隔离区域通过外延层与基板接触，但是不足以将未轰炸的基极区域驱动到这样的深度。
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2.发明授权
公开(公告)号：US4542579A
公开(公告)日：1985-09-24
申请号：US592150
申请日：1975-06-30
IPC分类号： H01L21/76 , H01L21/316 , H01L21/762 , H01L21/20
CPC分类号： H01L21/76227 , H01L21/31687 , Y10S148/085 , Y10S148/117
摘要： In the fabrication of integrated circuits, a method is provided for forming dielectrically isolated regions in a semiconductor substrate comprising forming over the semiconductor substrate surface an electrically insulating layer of dielectric material having a plurality of openings therethrough and etching to form recesses in the semiconductor substrate exposed in the openings. Then, aluminum is deposited over the substrate so that an aluminum layer is formed on said layer of dielectric material as well as in said recesses. Next, the aluminum in the recesses is selectively anodized to form aluminum oxide, and the remaining aluminum on said layer of dielectric material is removed either by selectively etching away the aluminum layer or by a "lift-off" technique wherein the insulating layer of dielectric material under the aluminum is etched away thereby "lifting-off" and removing the aluminum.
摘要翻译： 在集成电路的制造中，提供了一种用于在半导体衬底中形成介电隔离区域的方法，包括在半导体衬底表面上形成具有多个开口的介电材料的电绝缘层，并蚀刻以在半导体衬底中形成凹陷 在开口。 然后，在基板上沉积铝，使得在所述介电材料层以及所述凹部中形成铝层。 接下来，凹槽中的铝被选择性地阳极化以形成氧化铝，并且通过选择性地蚀刻掉铝层或通过“剥离”技术去除所述电介质材料层上的剩余的铝，其中电介质的绝缘层 铝下的材料被蚀刻掉，从而“脱落”并除去铝。
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公开(公告)号：US4303933A
公开(公告)日：1981-12-01
申请号：US98588
申请日：1979-11-29
IPC分类号： H01L21/76 , H01L21/331 , H01L21/74 , H01L21/762 , H01L29/08 , H01L29/10 , H01L29/73 , H01L29/732 , H01L27/04 , H01L29/72
CPC分类号： H01L21/743 , H01L21/76229 , H01L21/76232 , H01L29/0804 , H01L29/1004 , H01L29/7325 , Y10S148/131
摘要： A method for device fabrication disclosed is a self-aligned process. The device formed has small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls. The deep trench extends from the epitaxial silicon surface through N+ subcollector region into the P substrate. The width of the deep trench is about 2 .mu.m to 3.0 .mu.m. A shallow oxide trench extending from the epitaxial silicon surface to the upper portion of the N+ subcollector separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. As shown in FIG. 1, the fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter. This small base area results in low collector-base capacitance which is a very important parameter in ultra-high performance integrated circuit devices. Contact to the transistor base in the disclosed structure is achieved by a thick heavily boron doped polysilicon layer which surrounds the emitter and makes lateral contact to the active base.
摘要翻译： 公开的器件制造方法是自对准工艺。 形成的装置具有小的垂直和水平尺寸。 器件区域被具有几乎垂直侧壁的深氧化物沟槽围绕。 深沟槽从外延硅表面通过N +子集电极区域延伸到P衬底中。 深沟的宽度约为2〜3.0亩。 从外延硅表面延伸到N +子集电极的上部的浅氧化物沟槽分离基极和集电极触点。 隔离区域和形成晶体管的硅的表面是共面的。 如图所示。 如图1所示，制造的双极晶体管具有台面型结构。 晶体管基极尺寸仅略大于发射极。 这种小的基极面积导致集电极电容低，这是超高性能集成电路器件中非常重要的参数。 所公开的结构中与晶体管基极的接触是通过围绕发射极的厚的重硼掺杂的多晶硅层实现的，并且与活性基底进行横向接触。
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4.发明授权Anodic etching method for the detection of electrically active defects in silicon 失效用于检测硅中的电活性缺陷的阳极蚀刻方法
公开(公告)号：US4180439A
公开(公告)日：1979-12-25
申请号：US818476
申请日：1977-07-25
IPC分类号： G01N27/00 , G01R31/26 , G01R31/265 , G01N27/46
CPC分类号： G01R31/265 , G01R31/2637
摘要： Electrically active defects, i.e., current-carrying defects or leakage paths in silicon crystals, are detected by an anodization process. The process selectively etches the crystal surface only where the electrically active defects are located when the anodization parameters are properly selected. Selected surface portions of the silicon structure are exposed to a hydrofluoric acid solution which is maintained at a negative potential with respect to the silicon structure. When the potential difference is set to a proper value, etch pits are formed in the surface of the silicon only at those locations overlying electrically active defects which impact device yield. The defects are observed and counted to provide a basis to predict yield of desired semi-conductor devices to be formed later in the silicon structure.
摘要翻译： 通过阳极氧化处理检测电活性缺陷，即硅晶体中的载流缺陷或泄漏路径。 当阳极氧化参数被适当地选择时，该过程选择性地蚀刻仅在电活性缺陷所在的晶体表面。 硅结构的选定表面部分暴露于相对于硅结构保持在负电位的氢氟酸溶液。 当电位差被设定为适当的值时，仅在覆盖电活性缺陷的那些位置处形成硅的表面，这会影响器件的产量。 观察和计数缺陷以提供预测在硅结构中稍后形成的期望的半导体器件的产量的基础。
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5.发明授权
公开(公告)号：US4333227A
公开(公告)日：1982-06-08
申请号：US224705
申请日：1981-01-12
IPC分类号： H01L21/331 , H01L21/74 , H01L21/762 , H01L21/8222 , H01L29/08 , H01L29/10 , H01L29/732 , H01L21/302 , H01L21/31
CPC分类号： H01L29/66272 , H01L21/743 , H01L21/76229 , H01L21/76232 , H01L21/8222 , H01L29/0804 , H01L29/1004 , H01L29/7325 , Y10S148/131 , Y10S438/911 , Y10S438/981
摘要： A method for device fabrication utilizing a self-aligned process. A combination of advanced semiconductor processing techniques including Deep Dielectric Isolation by reactive-ion etching, etching and refilling, planarizing with oxides and resists, and differential thermal oxidation are used to form devices having small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls which extend from the epitaxial silicon surface through the N+ subcollector region into the P substrate. The width of the deep trench is about 2 .mu.m to 3 .mu.m. A shallow oxide trench extends from the epitaxial silicon surface to the upper portion of the N+ subcollector and separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. As shown in FIG. 1, the fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter. This small base area results in a low collector-base capacitance which is a very important parameter in ultra-high performance integrated circuit devices. Contact to the transistor base in the disclosed structure is achieved by a thick heavily boron doped polysilicon layer which is formed by an etch and refill process and which surrounds the emitter and makes lateral contact to the active base.
摘要翻译： 一种利用自对准工艺的器件制造方法。 采用先进的半导体处理技术，包括通过反应离子蚀刻的深层电介质隔离，蚀刻和再填充，用氧化物和抗蚀剂进行平面化以及差示热氧化的先进的半导体处理技术来形成具有小垂直和水平尺寸的器件。 器件区域由深氧化物沟槽围绕，其具有从外延硅表面通过N +子集电极区域延伸到P衬底的几乎垂直的侧壁。 深沟的宽度约为2〜3m。 浅氧化物沟槽从外延硅表面延伸到N +子集电极的上部，并分离基极和集电极触点。 隔离区域和形成晶体管的硅的表面是共面的。 如图所示。 如图1所示，制造的双极晶体管具有台面型结构。 晶体管基极尺寸仅略大于发射极。 这种小的基极面积导致集电极基极电容低，这是超高性能集成电路器件中非常重要的参数。 所公开的结构中与晶体管基极的接触是通过厚度很大的硼掺杂的多晶硅层实现的，该多晶硅层通过蚀刻和再填充工艺形成，并且围绕发射极并与活性基底进行横向接触。
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公开(公告)号：US20090170010A1
公开(公告)日：2009-07-02
申请号：US12006433
申请日：2007-12-31
CPC分类号： H01J37/3174 , B82Y10/00 , B82Y40/00 , G03F7/0002 , G11B5/855 , Y10S430/143
摘要： A high-resolution, patterned-media master mask is disclosed. The high-resolution, patterned-media master mask includes an electron-absorption substrate for absorbing electrons from an electron beam (e-beam) during an e-beam exposure by an e-beam lithography process and suppressing a backscattering of the electrons based on an electron-backscattering-suppressing atomic number associated with a constituent atomic species of the electron-absorption substrate, wherein the electron-absorption substrate comprises a material composed of greater than fifty atomic percent of the constituent atomic species, and wherein the electron backscattering-suppressing atomic number is less than an atomic number eight. The high-resolution, patterned-media master mask further includes a patterned portion coupled with the electron-absorption substrate, wherein the patterned portion is patterned by the e-beam lithography process, and wherein a resolution of the patterned portion is increased in response to the electron-absorption substrate suppressing the backscattering of the electrons.
摘要翻译： 公开了高分辨率图案化媒体主掩模。 高分辨率图案化媒体主掩模包括用于通过电子束光刻工艺在电子束曝光期间从电子束（电子束）吸收电子的电子吸收基板，并且基于以下原因抑制电子的反向散射 与电子吸收衬底的构成原子种类相关联的电子后向散射抑制原子序数，其中电子吸收衬底包括由组分原子种类大于50原子％组成的材料，并且其中电子后向散射抑制 原子数小于原子数8。 高分辨率图案化媒体主掩模还包括与电子吸收衬底耦合的图案部分，其中通过电子束光刻工艺对图案化部分进行构图，并且其中图案化部分的分辨率响应于 电子吸收衬底抑制电子的后向散射。
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公开(公告)号：US4378630A
公开(公告)日：1983-04-05
申请号：US309627
申请日：1981-10-08
IPC分类号： H01L21/331 , H01L21/762 , H01L21/8224 , H01L27/082 , H01L29/10 , H01L29/423 , H01L21/203 , H01L21/22
CPC分类号： H01L29/66272 , H01L21/76202 , H01L21/76229 , H01L21/76232 , H01L21/8224 , H01L27/0821 , H01L29/1004 , H01L29/42304
摘要： Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semiconductor chip. The base width of the lateral PNP transistor is very narrow (approximately 300 to 400 nanometers). This narrow dimension is in part obtained by using a well defined chemically vapor deposited (CVD) oxide mask instead of conventional lithographic masking. To eliminate the emitter current injecting into the substrate the P+ emitter and P+ collector of the PNP transistor are bounded by a silicon nitride and silicon dioxide dielectric layer.
摘要翻译： 公开了具有非常高的速度和低功率要求的PNP和NPN类型的非常小的集成电路器件的制造和结构。 该结构提供了在同一半导体芯片内形成的垂直NPN和横向PNP晶体管。 横向PNP晶体管的基极宽度非常窄（约300至400纳米）。 这个窄尺寸部分通过使用明确定义的化学气相沉积（CVD）氧化物掩模而不是常规的光刻掩模来获得。 为了消除注入衬底的发射极电流，PNP晶体管的P +发射极和P +集电极由氮化硅和二氧化硅介电层界定。
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公开(公告)号：US4338138A
公开(公告)日：1982-07-06
申请号：US126611
申请日：1980-03-03
申请人： Joseph R. Cavaliere , Cheng T. Horng , Richard R. Konian , Hans S. Rupprecht , Robert O. Schwenker
发明人： Joseph R. Cavaliere , Cheng T. Horng , Richard R. Konian , Hans S. Rupprecht , Robert O. Schwenker
IPC分类号： H01L21/8222 , H01L21/033 , H01L21/285 , H01L21/331 , H01L21/762 , H01L27/06 , H01L29/73 , H01L29/732 , H01L21/263 , H01L21/203 , H01L21/22 , H01L21/31
CPC分类号： H01L29/66272 , H01L21/033 , H01L21/28525 , H01L21/76229 , H01L21/76232 , H01L29/7325 , Y10S148/131
摘要： An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layers containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction. Also disclosed is a process and alternative process, for fabricating an improved bipolar transistor structure.
摘要翻译： 一种改进的双极晶体管结构，其形成在第一导电类型的硅衬底的平坦表面上的薄外延层的非常小的区域中，所述薄外延层的非常小的面积具有延伸到所述衬底的平坦表面的垂直侧壁， 所述薄外延层的区域包含按顺序列出的具有暴露平面的第二导电类型的浅深度发射极区域，所述第一导电类型的浅深度基底区域和所述第二导电类型的浅深度有源集电极区域 围绕所述发射极，基极和主动集电极区域的所述第一导电类型的细长区域，所述细长区域包含在所述薄外延层的所述小区域的所述垂直侧壁内并与之共同延伸，由此基极集电极电容由于 到基极 - 集电极结的非常小的区域。 还公开了用于制造改进的双极晶体管结构的工艺和替代工艺。
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9.发明授权Process for making large area isolation trenches utilizing a two-step selective etching technique 失效利用两步选择性蚀刻技术制造大面积隔离沟槽的方法
公开(公告)号：US4211582A
公开(公告)日：1980-07-08
申请号：US52997
申请日：1979-06-28
IPC分类号： H01L21/76 , H01L21/033 , H01L21/263 , H01L21/302 , H01L21/3065 , H01L21/316 , H01L21/762 , H01L21/768 , H01L21/306
CPC分类号： H01L21/0337 , H01L21/2633 , H01L21/3065 , H01L21/76208 , H01L21/76229 , H01L21/768 , H01L21/76877 , Y10S148/05 , Y10S148/051 , Y10S148/085 , Y10S148/106 , Y10S148/111 , Y10S148/131
摘要： A method for making wide, deep recessed oxide isolation trenches in silicon semiconductor substrates. A semi-conductor substrate is selectively etched to produce a spaced succession of narrow, shallow trenches separated by narrow silicon mesas. Silicon oxide is chemical-vapor-deposited on the horizontal and vertical surfaces of the etched structure to a thickness equalling the width of a desired silicon oxide mask. The mask is used for etching multiple deep trenches in the substrate, the trenches being separated by thin walls of silicon. The thickness of the walls is uniformly equal to and determined by the thickness of the deposited silicon oxide mask.The deposited silicon oxide is reactively ion etched away from the horizontal surfaces, leaving the oxide only on the sidewalls of the shallow trenches. The silicon is deeply etched, using the remaining oxide as a mask. Boron is ion implanted and the resulting structure is thermally oxidized sufficiently to completely oxidize the silicon under the deposited oxide mask and to oxidize the silicon surfaces at the bottoms of the trenches. The remaining trench volume is filled in with chemical-vapor-deposited silicon dioxide.
摘要翻译： 一种用于在硅半导体衬底中制造宽的深凹陷氧化物隔离沟槽的方法。 选择性地蚀刻半导体衬底以产生由狭窄的硅台面分开的间隔一连串的窄的浅沟槽。 氧化硅在蚀刻结构的水平和垂直表面上化学气相沉积到等于所需氧化硅掩模宽度的厚度。 掩模用于蚀刻衬底中的多个深沟槽，沟槽被薄壁的硅分隔开。 壁的厚度均匀地等于并由沉积的氧化硅掩模的厚度确定。 沉积的氧化硅被离子蚀刻离开水平表面，仅将氧化物留在浅沟槽的侧壁上。 硅被深刻蚀刻，使用剩余的氧化物作为掩模。 硼离子注入，并且所得结构被充分热氧化以在沉积的氧化物掩模下完全氧化硅，并在沟底部氧化硅表面。 剩余的沟槽体积填充有化学气相沉积的二氧化硅。
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10.发明授权
公开(公告)号：US5271802A
公开(公告)日：1993-12-21
申请号：US987509
申请日：1992-12-07
CPC分类号： G11B5/3106 , G11B5/6005 , Y10T29/49052
摘要： A method for making a magnetic head slider having a protective coating on the rails thereof, the protective coating containing a thin adhesion layer, a thin layer of amorphous hydrogenated carbon, and a thin masking layer. The protective coating is deposited on the air bearing surface of the slider after the thin film magnetic heads are lapped to a chosen dimension, but before the pattern of rails is produced on the air bearing surface. The protective coating protects the magnetic head during the rail fabrication process and in usage in a magnetic recording system protects the magnetic head from wear and corrosion damage.
摘要翻译： 一种用于制造在其轨道上具有保护涂层的磁头滑块的方法，所述保护涂层包含薄粘合层，非晶氢化碳薄层和薄掩蔽层。 在将薄膜磁头研磨成选定的尺寸之后，但是在空气轴承表面上产生轨道图案之前，保护涂层沉积在滑块的空气支承表面上。 保护涂层在轨道制造过程中保护磁头，并且在磁记录系统中使用可保护磁头免受磨损和腐蚀的损害。
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