公开(公告)号：US20200006269A1

公开(公告)日：2020-01-02

申请号：US16562434

申请日：2019-09-05

申请人： Samsung Electronics Co., Ltd.

发明人： Yi-Koan HONG ,  Kwang-Jin MOON ,  Nae-In LEE ,  Ho-Jin LEE

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/00

摘要： A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

公开(公告)号：US20220108962A1

公开(公告)日：2022-04-07

申请号：US17551548

申请日：2021-12-15

申请人： Samsung Electronics Co., Ltd.

发明人： Jeong-gi JIN ,  Nae-in LEE ,  Jum-yong PARK ,  Jin-ho CHUN ,  Seong-min SON ,  Ho-Jin LEE

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10

摘要： A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

公开(公告)号：US20180119302A1

公开(公告)日：2018-05-03

申请号：US15797472

申请日：2017-10-30

申请人： Samsung Electronics Co., Ltd.

发明人： Dong-Chan LIM ,  Kwang-Jin MOON ,  Byung-Lyul PARK ,  Nae-In LEE ,  Ho-Jin LEE

IPC分类号： C25D5/00 ,  C25D7/12 ,  C25D17/00 ,  C25D21/12 ,  H01L21/288 ,  H01L21/768

CPC分类号： C25D5/006 ,  C25D7/123 ,  C25D17/001 ,  C25D17/005 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76873 ,  H01L21/76877

摘要： An electroplating apparatus includes an electroplating bath including an anode installed therein and a plating solution received therein, a substrate holder configured to hold a substrate to be submerged into the plating solution and including a support surrounding the substrate and a cathode on the support to be electrically connected to a periphery of the substrate, a magnetic field generating assembly provided in the support and including at least one electromagnetic coil extending along a circumference of the substrate, and a power supply configured to current to the electromagnetic coil.

公开(公告)号：US20180053797A1

公开(公告)日：2018-02-22

申请号：US15630063

申请日：2017-06-22

申请人： Samsung Electronics Co., Ltd.

发明人： Ho-Jin LEE ,  Kwangjin MOON ,  Seokho KIM ,  Sukchul BANG ,  Jin Ho AN ,  Naein LEE

IPC分类号： H01L27/146

CPC分类号： H01L27/1463 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14683 ,  H01L2224/11

摘要： A semiconductor device includes a semiconductor substrate with first and second surfaces facing each other, an etch stop pattern in a trench formed in the first surface of the semiconductor substrate, a first insulating layer on the first surface of the semiconductor substrate, and a through via penetrating the semiconductor substrate and the first insulating layer. The etch stop pattern surrounds a portion of a lateral surface of the through via.

公开(公告)号：US20190067228A1

公开(公告)日：2019-02-28

申请号：US16052383

申请日：2018-08-01

申请人： Samsung Electronics Co., Ltd.

发明人： Seong-Min SON ,  Jeong-Gi JIN ,  Jin-Ho AN ,  Jin-Ho CHUN ,  Kwang-Jin MOON ,  Ho-Jin LEE

IPC分类号： H01L23/00 ,  H01L23/522 ,  H01L23/485

摘要： A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

公开(公告)号：US20160155686A1

公开(公告)日：2016-06-02

申请号：US14953857

申请日：2015-11-30

申请人： Samsung Electronics Co., Ltd.

发明人： Ho-Jin LEE ,  Byunglyul PARK ,  Jisoon PARK ,  Jinho AN

IPC分类号： H01L23/48 ,  H01L23/31 ,  H01L23/29 ,  H01L23/522 ,  H01L23/00 ,  H01L23/528

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/92 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/03845 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05016 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05556 ,  H01L2224/05559 ,  H01L2224/05564 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/0601 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/16146 ,  H01L2224/92 ,  H01L2924/13091 ,  H01L2924/381 ,  H01L2924/00012 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01028 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2224/03444 ,  H01L2224/0346 ,  H01L2224/03 ,  H01L21/304

摘要： Semiconductor devices are provided. The semiconductor devices include a substrate, a first interlayer insulating layer disposed on a front-side of the substrate, a TSV structure passing through the first interlayer insulating layer and the substrate. The TSV structure has a bottom end protruding from a back-side of the substrate, a back-side insulating layer and a back-side passivation layer disposed on the back-side of the substrate, and a bumping pad buried in the back-side insulating layer and the back-side passivation layer and disposed on the bottom end of the TSV structure. The bottom end of the TSV structure protrudes into the back-side bumping pad, and top surfaces of the back-side passivation layer and the back-side bumping pad are coplanar.

摘要翻译： 提供半导体器件。 半导体器件包括衬底，设置在衬底前侧的第一层间绝缘层，穿过第一层间绝缘层和衬底的TSV结构。 TSV结构具有从基板的背面突出的底端，设置在基板的背面侧的背面绝缘层和背面侧钝化层，以及埋在背面侧的凸块 绝缘层和背面钝化层，并设置在TSV结构的底端。 TSV结构的底端突出到后侧凸块中，背面钝化层和后侧凸块的顶面是共面的。

公开(公告)号：US20180366671A1

公开(公告)日：2018-12-20

申请号：US15870922

申请日：2018-01-13

申请人： Samsung Electronics Co., Ltd.

发明人： Yi-Koan HONG ,  Kwang-Jin MOON ,  Nae-In LEE ,  Ho-Jin LEE

IPC分类号： H01L51/44 ,  H01L25/065 ,  H01L23/538 ,  H01L23/532 ,  B82Y99/00

CPC分类号： H01L51/444 ,  B82Y10/00 ,  B82Y99/00 ,  H01L21/768 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53276 ,  H01L23/5329 ,  H01L23/538 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L51/0048 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/05007 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05564 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05576 ,  H01L2224/05578 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05693 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/08057 ,  H01L2224/0807 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012

摘要： A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

公开(公告)号：US20180069956A1

公开(公告)日：2018-03-08

申请号：US15811570

申请日：2017-11-13

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Shi-Yun CHO ,  Ji-Hyun JUNG ,  Ho-Jin LEE ,  Young-Min LEE ,  Ho-Seong SEO ,  Youn-Ho CHOI

IPC分类号： H04M1/725 ,  G06F1/16 ,  G06F3/0488 ,  H04B1/3827

CPC分类号： H04M1/72519 ,  G06F1/163 ,  G06F3/0488 ,  H04B1/385 ,  H04M2250/22

摘要： A watch phone and a method for handling an incoming call using the watch phone are provided. In the watch phone, a display device includes a touch screen panel and a display, turns off the touch screen panel in a watch mode, turns on the touch screen panel in an idle mode or upon receipt of an incoming call, and displays at least two areas for call connection and call rejection, upon receipt of the incoming call. A single mode selection key selects one of the watch mode and the idle mode. A controller performs control operations so that the touch screen panel is turned off in the watch mode and is turned on in the idle mode or upon receipt of the incoming call, and connects or rejects the incoming call, when the at least two areas for call connection or call rejection, which are displayed upon receipt of the incoming call, are pointed to or dragged to.

公开(公告)号：US20230046450A1

公开(公告)日：2023-02-16

申请号：US17980355

申请日：2022-11-03

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Shi-Yun CHO ,  Ji-Hyun JUNG ,  Ho-Jin LEE ,  Young-Min LEE ,  Ho-Seong SEO ,  Youn-Ho CHOI

IPC分类号： H04M1/724 ,  G06F1/16 ,  H04B1/3827 ,  G06F3/0488

摘要： A watch phone and a method for handling an incoming call using the watch phone are provided. In the watch phone, a display device includes a touch screen panel and a display, turns off the touch screen panel in a watch mode, turns on the touch screen panel in an idle mode or upon receipt of an incoming call, and displays at least two areas for call connection and call rejection, upon receipt of the incoming call. A single mode selection key selects one of the watch mode and the idle mode. A controller performs control operations so that the touch screen panel is turned off in the watch mode and is turned on in the idle mode or upon receipt of the incoming call, and connects or rejects the incoming call, when the at least two areas for call connection or call rejection, which are displayed upon receipt of the incoming call, are pointed to or dragged to.

公开(公告)号：US20210005565A1

公开(公告)日：2021-01-07

申请号：US17029639

申请日：2020-09-23

申请人： Samsung Electronics Co., Ltd.

发明人： Seong-Min SON ,  Jeong-Gi JIN ,  Jin-Ho AN ,  Jin-Ho CHUN ,  Kwang-Jin MOON ,  Ho-Jin LEE

IPC分类号： H01L23/00 ,  H01L23/485 ,  H01L23/522

摘要： A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.