公开(公告)号：US20190139899A1

公开(公告)日：2019-05-09

申请号：US16240174

申请日：2019-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonha JUNG ,  Jongkook KIM ,  Bona BAEK ,  Heeseok LEE ,  Kyoungsei CHOI

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/10 ,  H01L23/552 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.

公开(公告)号：US20250157867A1

公开(公告)日：2025-05-15

申请号：US18883053

申请日：2024-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongkook KIM ,  Heungkyu KWON ,  Youngchul KIM ,  Choonheung LEE ,  Donghyun CHA ,  Junghwa KIM ,  Junso PAK ,  Kyounghoon LEE ,  Jaegwon JANG ,  Hangchul CHOI ,  Heejung CHOI ,  Kyojin HWANG

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/18 ,  H05K1/18 ,  H10B80/00

Abstract: A semiconductor package that includes an upper package including a first package substrate, a first semiconductor chip mounted on the first package substrate, and a first molding layer surrounding the first semiconductor chip; a printed circuit board (PCB) on which the upper package is mounted in a central region; and a stiffener positioned on a top surface of the PCB and including an opening. A top surface of the PCB contacts a bottom surface of the stiffener in at least part of edge regions of the PCB. In the central region of the PCB and in edge regions other than the at least part of edge regions of the PCB, a top surface of the PCB is apart from the bottom surface of the stiffener in a vertical direction, and the opening of the stiffener overlaps the upper package in the vertical direction.

公开(公告)号：US20220365132A1

公开(公告)日：2022-11-17

申请号：US17549005

申请日：2021-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kijae SONG ,  Jongkook KIM ,  Dongho LEE ,  Seonmi LEE

IPC: G01R31/28 ,  G01R1/04

Abstract: A test board for testing a semiconductor apparatus includes a first board configured to support a plurality of first Devices Under Test (DUTs) such that the plurality of first DUTs are mounted on the first board, a plurality of first inter-board connectors arranged on the first board, and a plurality of second boards stacked on the first board through the plurality of first inter-board connectors, each second board of the plurality of second boards having a surface configured to support a separate second DUT of a plurality of second DUTs such that the plurality of second DUTs are mounted on separate, respective second boards of the plurality of second board.

公开(公告)号：US20210407962A1

公开(公告)日：2021-12-30

申请号：US17154789

申请日：2021-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongwon KIM ,  Junmo KOO ,  Yeonjoo KIM ,  Yunhee KIM ,  Jongkook KIM ,  Doohwan LEE ,  Jeongho LEE

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a base substrate, an interposer package disposed on the base substrate, and first and second semiconductor chips disposed on the interposer package, the interposer package includes a first redistribution layer, a bridge chip including a bridge circuit, and a vertical connection structure including a plurality of wiring layers, and wherein each of the first semiconductor chip and the second semiconductor chip is electrically connected to the bridge circuit and the plurality of wiring layers through the first redistribution layer.

公开(公告)号：US20250157958A1

公开(公告)日：2025-05-15

申请号：US18947424

申请日：2024-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongkook KIM ,  Heungkyu KWON ,  Junghwan JANG ,  Youngcheol KIM ,  Daehyun KIM ,  Choonheung LEE ,  Kwangho LEE ,  Hangchul CHOI

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package and a method of manufacturing the semiconductor package are provided. The semiconductor package includes an interposer, a semiconductor chip on the interposer, an under bump metal (UBM) pad between the interposer and the semiconductor chip and including an upper UBM pad and a lower UBM pad, and a connection member between the UBM pad and the semiconductor chip, wherein the connection member is in contact with one or more side surfaces of the UBM pad and is in contact with the interposer.

公开(公告)号：US20250046721A1

公开(公告)日：2025-02-06

申请号：US18592004

申请日：2024-02-29

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Choongbin YIM ,  Jongkook KIM ,  Chengtar WU

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package includes a support substrate having a through hole and including an insulating layer, one or more wiring layers including a first wiring layer, and a first electronic device on the first wiring layer, a semiconductor chip positioned in the through hole to be at least partially surrounded by the support substrate and including a connection pad on a first surface of the semiconductor chip, an encapsulant filling at least a portion of the through hole and encapsulating at least a portion of the semiconductor chip, a first redistribution layer structure on the first surface of the semiconductor chip and including a first redistribution layer, and a second redistribution layer structure over a second surface of the semiconductor chip that is opposite to the first surface of the semiconductor chip, the second redistribution layer structure including a second redistribution layer.

公开(公告)号：US20240258222A1

公开(公告)日：2024-08-01

申请号：US18493234

申请日：2023-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chengtar WU ,  Jongkook KIM ,  Choongbin YIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/15311

Abstract: A 3D integrated circuit structure, comprising: a redistribution layer structure; a first semiconductor chip die on the redistribution layer structure; a plurality of sacrificial pads on the redistribution layer structure; a plurality of conductive posts disposed adjacent the first semiconductor chip die, wherein the plurality of conductive posts is on the plurality of sacrificial pads, respectively; a molding material that is on the first semiconductor chip die, the plurality of sacrificial pads, the plurality of conductive posts, and the redistribution layer structure; an interconnection structure on the molding material; and a second semiconductor chip die on the interconnection structure, wherein the second semiconductor chip die overlaps the first semiconductor chip die and the plurality of conductive posts in a vertical direction.

公开(公告)号：US20240258221A1

公开(公告)日：2024-08-01

申请号：US18493166

申请日：2023-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongbin YIM ,  Jongkook KIM ,  Chengtar WU

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/08 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81

Abstract: A 3D integrated circuit structure includes a redistribution layer structure; a first semiconductor chip die on the redistribution layer structure; a plurality of core balls on the redistribution layer structure and adjacent the first semiconductor chip die; a molding material encapsulating the first semiconductor chip die and the plurality of core balls on the redistribution layer structure; an interconnection structure on the molding material; and a second semiconductor chip die on the interconnection structure. A footprint of the first semiconductor chip die and footprints of the plurality of core balls are within a footprint of the second semiconductor chip die.

公开(公告)号：US20240379635A1

公开(公告)日：2024-11-14

申请号：US18601335

申请日：2024-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongbin YIM ,  Jongkook KIM ,  Chengtar WU

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L23/28 ,  H01L23/498 ,  H01L25/00

Abstract: Provided a three-dimensional (3D) integrated circuit structure including a redistribution structure, a first semiconductor die on the redistribution structure, a substrate on the redistribution structure and adjacent to the first semiconductor die, a molding material on the redistribution structure and between the first semiconductor die and the substrate, an interconnection structure on the substrate and the first semiconductor die, the interconnection structure including a plurality of first bonding pads and a plurality of second bonding pads, and each second bonding pad of the second bonding pads being directly bonded to each first bonding pad of the first bonding pads, and a second semiconductor die on the interconnection structure.

公开(公告)号：US20160329285A1

公开(公告)日：2016-11-10

申请号：US15215227

申请日：2016-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonha JUNG ,  Jongkook KIM ,  Bona BAEK ,  Heeseok LEE ,  Kyoungsei CHOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/552

CPC classification number: H01L23/5389 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/3224 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83424 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83471 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.