公开(公告)号：US20230326970A1

公开(公告)日：2023-10-12

申请号：US18050684

申请日：2022-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namkyu CHO ,  Seokhoon KIM ,  Jeongho YOO ,  Choeun LEE ,  Pankwi PARK ,  Dongsuk SHIN

IPC: H01L29/08 ,  H01L29/786 ,  H01L27/092 ,  H01L29/66 ,  H01L29/775 ,  H01L29/40 ,  H01L29/423 ,  H01L29/417 ,  H01L21/8238

CPC classification number: H01L29/0847 ,  H01L29/78696 ,  H01L27/092 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/41783 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/0673

Abstract: A semiconductor device includes a substrate including a first active pattern, a first channel pattern on the first active pattern, the first channel pattern including first, second, and third semiconductor patterns spaced apart from one another and vertically stacked, a first source/drain pattern connected to the first to third semiconductor patterns, and a gate electrode on the first to third semiconductor patterns. The first source/drain pattern includes a first protrusion protruding toward the first semiconductor pattern, a second protrusion protruding toward the second semiconductor pattern, and a third protrusion protruding toward the third semiconductor pattern. A width of the second protrusion is greater than a width of the first protrusion. A width of the third protrusion is greater than the width of the second protrusion.

公开(公告)号：US20170092767A1

公开(公告)日：2017-03-30

申请号：US15379190

申请日：2016-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keum Seok PARK ,  Jungho YOO ,  Jinyeong JOE ,  Bonyoung KOO ,  Dongsuk SHIN ,  Hongsik YOON ,  Byeongchan LEE

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165 ,  H01L29/45

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02636 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.

公开(公告)号：US20200303523A1

公开(公告)日：2020-09-24

申请号：US16889899

申请日：2020-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Chan SUH ,  Sangmoon LEE ,  Yihwan KIM ,  Woo Bin SONG ,  Dongsuk SHIN ,  Seung Ryul LEE

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/786 ,  H01L29/423

Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.

公开(公告)号：US20190067285A1

公开(公告)日：2019-02-28

申请号：US15939914

申请日：2018-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmoon LEE ,  Jungtaek KIM ,  Yihwan KIM ,  Woo Bin SONG ,  Dongsuk SHIN ,  Seung Ryul LEE

IPC: H01L27/092 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a substrate; an active pattern spaced apart from the substrate and extending in a first direction; and a gate structure on the active pattern and extending in a second direction crossing the first direction, wherein a lower portion of the active pattern extends in the first direction and includes a first lower surface that is sloped with respect to an upper surface of the substrate.

公开(公告)号：US20230231049A1

公开(公告)日：2023-07-20

申请号：US17889744

申请日：2022-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongsuk SHIN ,  Hyun-Kwan Yu ,  Sunyoung Lee ,  Ji Hoon Cha ,  Kyungyeon Hwang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/783 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/512

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns, and a gate dielectric layer between the gate electrode and the semiconductor patterns. An inner spacer of the gate dielectric layer includes a horizontal portion between the high-k dielectric layer and the second semiconductor pattern, a vertical portion between the high-k dielectric layer and the source/drain pattern, and a corner portion between the horizontal portion and the vertical portion. A first thickness of the horizontal portion is less than a second thickness of the vertical portion. The second thickness of the vertical portion is less than a third thickness of the corner portion.

公开(公告)号：US20230223405A1

公开(公告)日：2023-07-13

申请号：US18122253

申请日：2023-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee CHOI ,  Keunhwi CHO ,  Myunggil KANG ,  Seokhoon KIM ,  Dongwon KIM ,  Pankwi PARK ,  Dongsuk SHIN

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/167 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/66439

Abstract: An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x≠0, and the inner blocking layer including a Si layer.

公开(公告)号：US20190081160A1

公开(公告)日：2019-03-14

申请号：US15956166

申请日：2018-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Chan SUH ,  Sangmoon LEE ,  Yihwan KIM ,  Woo Bin SONG ,  Dongsuk SHIN ,  Seung Ryul LEE

IPC: H01L29/66 ,  H01L21/28

Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.

公开(公告)号：US20240153954A1

公开(公告)日：2024-05-09

申请号：US18414039

申请日：2024-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee CHOI ,  Keunhwi CHO ,  Myunggil KANG ,  Seokhoon KIM ,  Dongwon KIM ,  Pankwi PARK ,  Dongsuk SHIN

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851

Abstract: An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x≠0, and the inner blocking layer including a Si layer.

公开(公告)号：US20230007959A1

公开(公告)日：2023-01-12

申请号：US17804102

申请日：2022-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyeong JOE ,  Dongchan SUH ,  Sungkeun LIM ,  Seokhoon KIM ,  Pankwi PARK ,  Dongsuk SHIN

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a first active region, a second active region spaced apart from the first active region, a plurality of first channel layers disposed on the first active region, and a second channel layer disposed on the second active region. The semiconductor device further includes a first gate structure intersecting the first active region and the first channel layers, a second gate structure intersecting the second active region and the second channel layer, a first source/drain region disposed on the first active region and contacting the plurality of first channel layers, and a second source/drain region and contacting the second channel layer. The plurality of first channel layers includes a first uppermost channel layer and first lower channel layers disposed below the first uppermost channel layer, and the first uppermost channel layer includes a material that is different from a material included in the first lower channel layers.

公开(公告)号：US20140312430A1

公开(公告)日：2014-10-23

申请号：US14318957

申请日：2014-06-30

Applicant: SAMSUNG Electronics Co., Ltd.

Inventor： Dong Hyuk KIM ,  Dongsuk SHIN ,  Myungsun KIM ,  Hoi Sung CHUNG

IPC: H01L29/78 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/02057 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/088 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66636

Abstract: A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.

Abstract translation: 制造一个或多个半导体器件的方法包括在半导体衬底中形成沟槽，执行循环过程以从沟槽去除污染物，以及在沟槽上形成外延层。 循环过程包括将含有锗烷，氯化氢和氢的第一反应气体和含有氯化氢和氢的第二反应气体依次提供到半导体衬底上。