公开(公告)号：US09752643B2

公开(公告)日：2017-09-05

申请号：US14652055

申请日：2013-12-06

申请人： SHANGHAI MICRO ELECTRONICS EQUIPMENT CO., LTD. ,  TSINGHUA UNIVERSITY

发明人： Yu Zhu ,  Ming Zhang ,  Zhao Liu ,  Rong Cheng ,  Jing Wang ,  Li Tian ,  Dengfeng Xu ,  Kaiming Yang ,  Jinchun Hu ,  Wensheng Yin ,  Haihua Mu ,  Hao Liu ,  Chuxiong Hu

IPC分类号： F16F15/067 ,  G03F7/20

CPC分类号： F16F15/067 ,  F16F2228/063 ,  G03F7/70 ,  G03F7/70716 ,  G03F7/70816 ,  G03F7/709

摘要： A negative stiffness system for gravity compensation of a micropositioner of wafer table in lithography machine, characterized in that, the negative stiffness system includes at least three sets of quasi-zero stiffness units, each of the sets of quasi-zero stiffness units comprises a pair of negative stiffness springs and a positive stiffness spring, the positive stiffness spring is vertically positioned, the pair of negative stiffness springs are obliquely and symmetrically positioned at two sides of the positive stiffness spring, upper ends of the negative stiffness springs and the positive stiffness spring are connected together and fixed to the bottom surface of a rotor of the micropositioner, and lower ends of the negative stiffness springs and the positive stiffness spring are connected to a base, respectively. The system reduces the stiffness in vertical direction and prevents the influence of permanent magnet on its surroundings, while improving the bearing capacity.

公开(公告)号：US20150243502A1

公开(公告)日：2015-08-27

申请号：US14347930

申请日：2014-03-18

申请人： Tsinghua University

发明人： Jing Wang ,  Lei Xiao ,  Mei Zhao ,  Renrong Liang ,  Jun Xu

IPC分类号： H01L21/02 ,  H01L29/161 ,  H01L21/479 ,  H01L29/66

CPC分类号： H01L21/02694 ,  H01L21/02631 ,  H01L21/479 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795

摘要： A method for forming a fin field effect transistor is provided. The method includes: providing a substrate; forming a fin structure with a material Ge or GeSi on the substrate; implanting atoms, molecules, ions or plasmas containing an element Sn into the fin structure with the material Ge or GeSi to form a Ge-based GeSn layer or a Ge-based GeSnSi layer; and forming a gate stack on the Ge-based GeSn layer or the Ge-based GeSnSi layer, the gate stack being oriented transversely to the fin structure.

摘要翻译： 提供一种形成鳍式场效应晶体管的方法。 该方法包括：提供衬底; 在基板上形成具有Ge或GeSi的材料的翅片结构; 用材料Ge或GeSi将含有元素Sn的原子，分子，离子或等离子体注入到翅片结构中，以形成Ge基GeSn层或Ge基GeSnSi层; 并且在Ge基GeSn层或Ge基GeSnSi层上形成栅极堆叠，栅叠层横向于鳍结构。

公开(公告)号：US09105475B1

公开(公告)日：2015-08-11

申请号：US14347930

申请日：2014-03-18

申请人： Tsinghua University

发明人： Jing Wang ,  Lei Xiao ,  Mei Zhao ,  Renrong Liang ,  Jun Xu

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L29/66 ,  H01L29/161 ,  H01L21/479

CPC分类号： H01L21/02694 ,  H01L21/02631 ,  H01L21/479 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795

摘要： A method for forming a fin field effect transistor is provided. The method includes: providing a substrate; forming a fin structure with a material Ge or GeSi on the substrate; implanting atoms, molecules, ions or plasmas containing an element Sn into the fin structure with the material Ge or GeSi to form a Ge-based GeSn layer or a Ge-based GeSnSi layer; and forming a gate stack on the Ge-based GeSn layer or the Ge-based GeSnSi layer, the gate stack being oriented transversely to the fin structure.

摘要翻译： 提供一种形成鳍式场效应晶体管的方法。 该方法包括：提供衬底; 在基板上形成具有Ge或GeSi的材料的翅片结构; 用材料Ge或GeSi将含有元素Sn的原子，分子，离子或等离子体注入到翅片结构中，以形成Ge基GeSn层或Ge基GeSnSi层; 并且在Ge基GeSn层或Ge基GeSnSi层上形成栅极堆叠，栅叠层横向于鳍结构。

公开(公告)号：US08963295B2

公开(公告)日：2015-02-24

申请号：US13816164

申请日：2012-12-18

申请人： Tsinghua University

发明人： Jing Wang ,  Renrong Liang ,  Lei Guo ,  Jun Xu

IPC分类号： H01L27/12 ,  H01L21/00 ,  H01L29/10 ,  H01L29/04 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L21/8238 ,  H01L21/027

CPC分类号： H01L29/04 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/0276 ,  H01L21/28255 ,  H01L21/823807 ,  H01L29/06 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/24 ,  H01L29/517 ,  H01L29/78

摘要： A semiconductor structure with beryllium oxide is provided. The semiconductor structure comprises: a semiconductor substrate (100); and a plurality of insulation oxide layers (201, 202 . . . 20x) and a plurality of single crystal semiconductor layers (301, 302 . . . 30x) alternately stacked on the semiconductor substrate (100). A material of the insulation oxide layer (201) contacted with the semiconductor substrate (100) is any one of beryllium oxide, SiO2, SiOxNy and a combination thereof, a material of other insulation oxide layers (202 . . . 20x) is single crystal beryllium oxide.

摘要翻译： 提供了具有氧化铍的半导体结构。 半导体结构包括：半导体衬底（100）; 以及交替层叠在半导体基板（100）上的多个绝缘氧化物层（201,202,20.0x）和多个单晶半导体层（301,302,30 ...）。 与半导体衬底（100）接触的绝缘氧化物层（201）的材料是氧化铍，SiO 2，SiO x N y及其组合中的任一种，其它绝缘氧化物层（202.20x）的材料是单晶 氧化铍。

公开(公告)号：US10388750B2

公开(公告)日：2019-08-20

申请号：US15305240

申请日：2016-06-03

申请人： Tsinghua University

发明人： Xian Wu ,  Lei Guo ,  Jing Wang

IPC分类号： H01L33/00 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/04 ,  H01L29/40 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/20

摘要： A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes: a substrate, at least a part of an upper surface of the substrate being a nonpolar surface or a semi-polar surface including nitride semiconductor crystals; an interface layer formed on the nonpolar surface or the semi-polar surface, and including at least one selected from a nitride and an oxynitride; and a metal layer formed on a surface of the interface layer away from the substrate.

公开(公告)号：US09299566B2

公开(公告)日：2016-03-29

申请号：US14350715

申请日：2014-03-21

申请人： Tsinghua University

发明人： Lei Xiao ,  Jing Wang ,  Mei Zhao ,  Renrong Liang ,  Jun Xu

IPC分类号： H01L21/223 ,  H01L21/265 ,  H01L21/285

CPC分类号： H01L21/26513 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02614 ,  H01L21/02631 ,  H01L21/223 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/28255 ,  H01L21/28512 ,  H01L29/161

摘要： A method for forming a germanium-based layer is provided. The method includes: providing a substrate having a Ge or GeSi surface layer; and implanting atoms, molecules, ions or plasmas containing an element Sn into the Ge surface layer to form a Ge-based GeSn layer, or implanting atoms, molecules, ions or plasmas containing an element Sn into the GeSi surface layer to form a Ge-based GeSnSi layer, or co-implanting atoms, molecules, ions or plasmas containing elements Sn and Si into the Ge surface layer to form a Ge-based GeSnSi layer.

摘要翻译： 提供了形成锗基层的方法。 该方法包括：提供具有Ge或GeSi表面层的衬底; 并将含有元素Sn的原子，分子，离子或等离子体注入到Ge表面层中以形成Ge基GeSn层，或将含有元素Sn的原子，分子，离子或等离子体注入到GeSi表面层中以形成Ge- 或者将含有元素Sn和Si的原子，分子，离子或等离子体共注入到Ge表面层中以形成Ge基GeSnSi层。

公开(公告)号：US20150243505A1

公开(公告)日：2015-08-27

申请号：US14350677

申请日：2014-03-21

申请人： Tsinghua University

发明人： Jing Wang ,  Lei Xiao ,  Mei Zhao ,  Reneong Liang ,  Jun Xu

IPC分类号： H01L21/265 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L29/6681 ,  H01L21/26506 ,  H01L21/28255 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848

摘要： A method for forming a FinFET is provided, comprising: providing a substrate; forming a fin structure with a material Ge or GeSi on the substrate; forming a gate stack or a dummy gate on the substrate; defining a first region and a second region in the fin structure; and implanting atoms, molecules, ions or plasmas containing an element Sn into the first region and the second region in the fin structure with the material Ge to form a strained GeSn layer, or implanting atoms, molecules, ions or plasmas containing an element Sn into the first region and the second region in the fin structure with the material GeSi to form a strained GeSnSi layer, or co-implanting atoms, molecules, ions or plasmas containing elements Sn and Si into the first region and the second region in the fin structure with the material GeSi to form a strained GeSnSi layer.

摘要翻译： 提供一种形成FinFET的方法，包括：提供衬底; 在基板上形成具有Ge或GeSi的材料的翅片结构; 在基板上形成栅叠层或虚栅; 限定所述翅片结构中的第一区域和第二区域; 以及将含有元素Sn的原子，分子，离子或等离子体注入第一区域和鳍状结构中的第二区域与材料Ge形成应变GeSn层，或将含有元素Sn的原子，分子，离子或等离子体注入 翅片结构中的第一区域和第二区域，其中材料GeSi以形成应变的GeSnSi层，或将含有元素Sn和Si的原子，分子，离子或等离子体共注入到鳍状结构中的第一区域和第二区域 与GeSi材料形成应变的GeSnSi层。

公开(公告)号：US09105464B2

公开(公告)日：2015-08-11

申请号：US13816173

申请日：2012-12-18

申请人： Tsinghua University

发明人： Jing Wang ,  Renrong Liang ,  Lei Guo ,  Jun Xu

IPC分类号： H01L29/02 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H01L29/10 ,  H01L29/161

CPC分类号： H01L29/02 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/28255 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/517 ,  H01L29/78

摘要： A semiconductor structure with a rare earth oxide is provided. The semiconductor structure comprises: a semiconductor substrate (100); and a plurality of insulation oxide layers (201, 202 . . . 20x) and a plurality of single crystal semiconductor layers (301, 302 . . . 30x) alternately stacked on the semiconductor substrate (100). A material of the insulation oxide layer (201) contacted with the semiconductor substrate (100) is any one of a rare earth oxide, SiO2, SiOxNy and a combination thereof, a material of other insulation oxide layers (202 . . . 20x) is a single crystal rare earth oxide.

摘要翻译： 提供了具有稀土氧化物的半导体结构。 半导体结构包括：半导体衬底（100）; 以及交替层叠在半导体基板（100）上的多个绝缘氧化物层（201,202,20.0x）和多个单晶半导体层（301,302,30 ...）。 与半导体衬底（100）接触的绝缘氧化物层（201）的材料是稀土氧化物，SiO 2，SiO x N y及其组合中的任一种，其它绝缘氧化物层（202.0×20×）的材料为 单晶稀土氧化物。

公开(公告)号：US09159814B2

公开(公告)日：2015-10-13

申请号：US13983379

申请日：2013-05-31

申请人： Tsinghua University

发明人： Libin Liu ,  Jing Wang ,  Renrong Liang

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A memory structure and a method for forming the same are provided. The memory structure comprises: a substrate; a plurality of channel structures formed on the substrate, in which the plurality of channel structures are parallel with each other, each channel structure comprises a plurality of single crystal semiconductor layers and a plurality of oxide layers alternately stacked in a direction perpendicular to the substrate, and at least one of the plurality of oxide layers is a single crystal oxide layer; and a plurality of gate structures matched with the plurality of channel structures, in which each gate structure comprises a gate dielectric layer immediately adjacent to the plurality of channel structures and a gate electrode layer immediately adjacent to the gate dielectric layer.

摘要翻译： 提供了一种记忆结构及其形成方法。 存储器结构包括：衬底; 多个沟道结构，其形成在所述基板上，所述多个沟道结构彼此平行，每个沟道结构包括沿垂直于所述衬底的方向交替堆叠的多个单晶半导体层和多个氧化物层， 并且所述多个氧化物层中的至少一个是单晶氧化物层; 以及与多个沟道结构匹配的多个栅极结构，其中每个栅极结构包括与多个沟道结构紧邻的栅极电介质层和紧邻栅极电介质层的栅极电极层。

公开(公告)号：US08927966B2

公开(公告)日：2015-01-06

申请号：US13703722

申请日：2012-10-18

申请人： Tsinghua University

发明人： Libin Liu ,  Renrong Liang ,  Jing Wang ,  Jun Xu

IPC分类号： H01L31/00 ,  H01L29/78 ,  H01L29/66 ,  H01L27/108 ,  H01L21/84 ,  H01L29/775 ,  H01L27/12

CPC分类号： H01L29/775 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785

摘要： A dynamic random access memory unit and a method for fabricating the same are provided. The dynamic random access memory unit comprises: a substrate; an insulating buried layer formed on the substrate; a body region formed on the insulating buried layer and used as a charge storing region; two isolation regions formed on the body region, in which a semiconductor contact region is formed between the isolation regions and is a charge channel; a source, a drain and a channel region formed on the isolation regions and the semiconductor contact region respectively and constituting a transistor operating region which is partially separated from the charge storing region by the isolation regions and connected with the charge storing region via the charge channel; a gate dielectric layer formed on the transistor operating region, a gate formed on the gate dielectric layer; a source metal contact layer, a drain metal contact layer.

摘要翻译： 提供了动态随机存取存储单元及其制造方法。 动态随机存取存储器单元包括：衬底; 形成在基板上的绝缘掩埋层; 形成在绝缘掩埋层上并用作电荷存储区域的体区; 形成在体区的两个隔离区，其中在隔离区之间形成半导体接触区，并且是电荷通道; 分别形成在所述隔离区域和所述半导体接触区域上的源极，漏极和沟道区域，并且构成晶体管工作区域，所述晶体管工作区域由所述隔离区域部分地与所述电荷存储区域分离，并且经由所述充电沟道与所述电荷存储区域连接 ; 形成在所述晶体管工作区上的栅介质层，形成在所述栅介质层上的栅极; 源极金属接触层，漏极金属接触层。