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    Semiconductor die bonding structure
    2.
    发明授权
    Semiconductor die bonding structure 有权

    公开(公告)号：US11876052B2

    公开(公告)日：2024-01-16

    申请号：US17324973

    申请日：2021-05-19

    申请人： SK hynix Inc.

    发明人： Na Bin Won ,  Jong Hoon Kim

    IPC分类号： H01L23/04 ,  H01L23/538 ,  H01L25/065

    CPC分类号： H01L23/5384 ,  H01L23/5386 ,  H01L25/0657

    摘要： A semiconductor die bonding structure includes a lower die including a lower top bonding dielectric layer and a lower connection structure and an upper die stacked over the lower die and including an upper bottom bonding dielectric layer and an upper connection structure. The lower top bonding dielectric layer and the upper bottom bonding dielectric layer are connected. The lower connection structure and the upper connection structure are connected.

    Semiconductor devices having through electrodes and methods of manufacturing the same
    5.
    发明授权
    Semiconductor devices having through electrodes and methods of manufacturing the same 有权

    公开(公告)号：US10109545B2

    公开(公告)日：2018-10-23

    申请号：US15459592

    申请日：2017-03-15

    申请人： SK hynix Inc.

    发明人： Jong Kyu Moon ,  Jong Hoon Kim ,  Sung Su Park

    IPC分类号： H01L23/26 ,  H01L21/304 ,  H01L21/306 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L21/683

    摘要： Semiconductor devices are provided. The semiconductor device includes a semiconductor layer having a first surface and a second surface that are opposite each other, a through electrode penetrating the semiconductor layer and having a protrusion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed over the first surface of the semiconductor layer and electrically coupled to the through electrode, a polymer pattern disposed over the second surface of the semiconductor layer to enclose a part of the protrusion of the through electrode, and a back-side bump covering an upper surface and a sidewall of a remaining part of the protrusion of the through electrode and extending over a portion of the polymer pattern.

    Semiconductor package including stacked semiconductor chips
    9.
    发明授权
    Semiconductor package including stacked semiconductor chips 有权

    公开(公告)号：US11996392B2

    公开(公告)日：2024-05-28

    申请号：US18304106

    申请日：2023-04-20

    申请人： SK hynix Inc.

    发明人： Eun Hye Do ,  Jong Hoon Kim

    IPC分类号： H01L25/065

    CPC分类号： H01L25/0657 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586

    摘要： A semiconductor package includes: semiconductor chips being offset-stacked to expose edge regions adjacent to first side surfaces; chip pads disposed in each of the edge regions of the semiconductor chips, the chip pads including a plurality of first chip pads arranged in a first column and a plurality of second chip pads arranged in a second column; a horizontal common interconnector having one end connected to the second chip pad of a semiconductor chip of the semiconductor chips, and another end connected to the first chip pad of another semiconductor chip; and a vertical common interconnector having one end connected to the second chip pad of the uppermost semiconductor chip, which is electrically connected to the first chip pad of the uppermost semiconductor chip connected to the horizontal common interconnector.

    Semiconductor packages including bridge die
    10.
    发明授权
    Semiconductor packages including bridge die 有权

    公开(公告)号：US10991640B2

    公开(公告)日：2021-04-27

    申请号：US16545896

    申请日：2019-08-20

    申请人： SK hynix Inc.

    发明人： Jong Hoon Kim ,  Ki Bum Kim ,  Bok Kyu Choi

    IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00

    摘要： A semiconductor package includes a first semiconductor die and a stack of second semiconductor dies disposed on a package substrate. The semiconductor package further includes a first bridge die having first through vias that electrically connect the first semiconductor die to the package substrate, a second bridge die having second through vias that electrically connect the stack of the second semiconductor dies to the package substrate, and a third semiconductor die disposed to overlap with the first semiconductor die and the stack of the second semiconductor dies. Moreover, the semiconductor package further includes redistribution lines electrically connecting the third semiconductor die to the second bridge die.