公开(公告)号：US10014248B2

公开(公告)日：2018-07-03

申请号：US15316546

申请日：2015-06-05

Applicant: SONY CORPORATION

Inventor： Makoto Murai ,  Yuji Takaoka ,  Hiroyuki Yamada ,  Kazuki Sato ,  Makoto Imai

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13564 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/8112 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Provided is a semiconductor device that includes a semiconductor chip, and a packaging substrate on which the semiconductor chip is mounted. The semiconductor chip includes a chip body and a plurality of solder-including electrodes that are provided on an element-formation surface of the chip body. The packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The aperture has a planar shape elongated in a lengthwise direction of the wiring inside the aperture, with a length of the aperture adjusted in accordance with a thermal expansion coefficient of the packaging substrate.

公开(公告)号：US20150179614A1

公开(公告)日：2015-06-25

申请号：US14549792

申请日：2014-11-21

Applicant: Sony Corporation

Inventor： Makoto Murai

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45464 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/15313 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01013

Abstract: Provided is a semiconductor device, including: a first substrate that includes a first wiring; a second substrate that is disposed facing the first substrate and includes a second wiring, the second wiring being connected to the first wiring through a connection terminal, and the second substrate being smaller in area than the first substrate; a first resin layer that is filled in a gap between the first substrate and the second substrate and covers a region, on the first substrate, in an outer periphery of the second substrate; an organic film pattern that is provided on the first substrate and surrounds the first resin layer; and a second resin layer that covers the first substrate, the organic film pattern, the first resin layer, and the second substrate.

Abstract translation: 提供一种半导体器件，包括：第一衬底，其包括第一布线; 第二基板，其面对所述第一基板设置并且包括第二布线，所述第二布线通过连接端子连接到所述第一布线，并且所述第二基板的面积小于所述第一基板; 第一树脂层，其填充在第一基板和第二基板之间的间隙中，并且覆盖第二基板的外周中的第一基板上的区域; 有机膜图案，设置在第一基板上并且包围第一树脂层; 以及覆盖第一基板，有机膜图案，第一树脂层和第二基板的第二树脂层。

公开(公告)号：US11024757B2

公开(公告)日：2021-06-01

申请号：US16065972

申请日：2016-11-30

Applicant: SONY CORPORATION

Inventor： Makoto Murai

IPC: H01L31/10 ,  H01L31/024 ,  H01L27/14 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H01L25/00 ,  H01L31/0224 ,  H04N5/225 ,  H01L31/0203 ,  H01L27/146

Abstract: In the semiconductor device, a first package is provided with a first substrate under which a semiconductor chip configured to output a signal and a first wiring electrically connected to the semiconductor chip are arranged. A second package is provided with a second substrate above which a processing circuit configured to process the output signal, a second wiring electrically connected to the processing circuit, and an encapsulant configured to seal the processing circuit are arranged, the semiconductor chip and the encapsulant being arranged to face each other in a non-contact manner. A connection portion electrically connects the first wiring and the second wiring.

公开(公告)号：US09368480B2

公开(公告)日：2016-06-14

申请号：US14549792

申请日：2014-11-21

Applicant: Sony Corporation

Inventor： Makoto Murai

IPC: H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45464 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/15313 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01013

Abstract: Provided is a semiconductor device, including: a first substrate that includes a first wiring; a second substrate that is disposed facing the first substrate and includes a second wiring, the second wiring being connected to the first wiring through a connection terminal, and the second substrate being smaller in area than the first substrate; a first resin layer that is filled in a gap between the first substrate and the second substrate and covers a region, on the first substrate, in an outer periphery of the second substrate; an organic film pattern that is provided on the first substrate and surrounds the first resin layer; and a second resin layer that covers the first substrate, the organic film pattern, the first resin layer, and the second substrate.

Abstract translation: 提供一种半导体器件，包括：第一衬底，其包括第一布线; 第二基板，其面对所述第一基板设置并且包括第二布线，所述第二布线通过连接端子连接到所述第一布线，并且所述第二基板的面积小于所述第一基板; 第一树脂层，其填充在第一基板和第二基板之间的间隙中，并且覆盖第二基板的外周中的第一基板上的区域; 有机膜图案，设置在第一基板上并且包围第一树脂层; 以及覆盖第一基板，有机膜图案，第一树脂层和第二基板的第二树脂层。

公开(公告)号：US10720402B2

公开(公告)日：2020-07-21

申请号：US15316574

申请日：2015-06-05

Applicant: SONY CORPORATION

Inventor： Makoto Murai ,  Kazuki Sato ,  Hiroyuki Yamada ,  Yuji Takaoka ,  Makoto Imai ,  Shigeki Amano

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L25/065

Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and one or more conductive layers and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the one or more conductive layers, and has one or more apertures on each of the one or more conductive layers. The plurality of solder-including electrodes include two or more first electrodes having a same function other than a function of power supply. The one or more conductive layers include a continuous first conductive layer. The two or more first electrodes are connected to the continuous first conductive layer. The one or more apertures are confronted with the respective two or more first electrodes.

公开(公告)号：US10418340B2

公开(公告)日：2019-09-17

申请号：US15316640

申请日：2015-06-05

Applicant: SONY CORPORATION

Inventor： Makoto Murai ,  Yuji Takaoka ,  Kazuki Sato ,  Hiroyuki Yamada

IPC: H01L23/00 ,  H01L23/12 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/03 ,  H01L25/10 ,  H05K1/11 ,  H05K3/34 ,  H01L25/065 ,  H01L21/683

Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The plurality of solder-including electrodes include a plurality of first electrodes and a plurality of second electrodes. The plurality of first electrodes supply a first electric potential, and the plurality of second electrodes supply a second electric potential different from the first electric potential. The plurality of first electrodes and the plurality of second electrodes are disposed alternately in both a row direction and a column direction, in a central part of the chip body. The plurality of wirings include a plurality of first wirings and a plurality of second wirings. The plurality of first wirings connect the plurality of first electrodes, and the plurality of second wirings connect the plurality of second electrodes.