公开(公告)号：US08896133B2

公开(公告)日：2014-11-25

申请号：US13870928

申请日：2013-04-25

Applicant: STATS ChipPAC, Ltd.

Inventor： SungWon Cho ,  KiYoun Jang ,  YongHee Kang ,  Hyung Sang Park

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L24/09 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1155 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11903 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48158 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81011 ,  H01L2224/81022 ,  H01L2224/81024 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/8385 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/01014 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device.

Abstract translation: 半导体器件具有形成在第一衬底上的第一衬底和第一导电柱。 第二导电柱形成在第一基板上，与第一导电柱交替。 第二导电柱相对于第一导电柱垂直偏移。 第一BOT互连位点形成在第二基底上。 第二BOT互连位置形成在第二衬底上与第一互连位置交替。 第二互连站点相对于第一互连站点垂直偏移。 第一衬底安装到第二衬底，使得第一导电柱与第一互连位置对准并电连接，并且第二导电柱与第二互连位置对准并电连接到第二互连位置。 底部填充材料沉积在第一和第二基底之间。 第一基板可以是倒装芯片型半导体器件。

公开(公告)号：US20130234324A1

公开(公告)日：2013-09-12

申请号：US13870928

申请日：2013-04-25

Applicant: STATS CHIPPAC, LTD.

Inventor： SungWon Cho ,  KiYoun Jang ,  YongHee Kang ,  Hyung Sang Park

IPC: H01L23/00

CPC classification number: H01L24/09 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1155 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11903 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48158 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81011 ,  H01L2224/81022 ,  H01L2224/81024 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/8385 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/01014 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device.

Abstract translation: 半导体器件具有形成在第一衬底上的第一衬底和第一导电柱。 第二导电柱形成在第一基板上，与第一导电柱交替。 第二导电柱相对于第一导电柱垂直偏移。 第一BOT互连位点形成在第二基底上。 第二BOT互连位置形成在第二衬底上与第一互连位置交替。 第二互连站点相对于第一互连站点垂直偏移。 第一衬底安装到第二衬底，使得第一导电柱与第一互连位置对准并电连接，并且第二导电柱与第二互连位置对准并电连接到第二互连位置。 底部填充材料沉积在第一和第二基底之间。 第一基板可以是倒装芯片型半导体器件。