公开(公告)号：US09236332B2

公开(公告)日：2016-01-12

申请号：US13765594

申请日：2013-02-12

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  KiYoun Jang ,  HunTeak Lee

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05155 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48249 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure.

公开(公告)号：US09117812B2

公开(公告)日：2015-08-25

申请号：US14138382

申请日：2013-12-23

Applicant: STATS ChipPAC, Ltd.

Inventor： JaeHyun Lee ,  KiYoun Jang ,  KyungHoon Lee ,  TaeWoo Lee

IPC: H01L21/4763 ,  H01L23/12 ,  H01L23/498 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49816 ,  H01L21/4814 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76838 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5329 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A semiconductor device has a substrate and first conductive layer formed over the substrate. An insulating layer is formed over the first substrate with an opening over the first conductive layer. A second conductive layer is formed within the opening of the insulating layer. A portion of the second conductive layer is removed to expose a horizontal surface and side surfaces of the second conductive layer below a surface of the insulating layer. The second conductive layer has non-linear surfaces to extend a contact area of the second conductive layer. The horizontal surface and side surfaces can be stepped surfaces or formed as a ring. A third conductive layer is formed over the second conductive layer. A plurality of bumps is formed over the horizontal surface and side surfaces of the second conductive layer. A semiconductor die is mounted to the substrate.

Abstract translation: 半导体器件具有衬底和形成在衬底上的第一导电层。 绝缘层在第一基板的上方形成有第一导电层上的开口。 第二导电层形成在绝缘层的开口内。 去除第二导电层的一部分以暴露第二导电层在绝缘层的表面下方的水平表面和侧表面。 第二导电层具有非线性表面以延伸第二导电层的接触面积。 水平表面和侧表面可以是台阶表面或形成为环形。 在第二导电层上形成第三导电层。 在第二导电层的水平表面和侧表面上形成多个凸块。 将半导体管芯安装到基板上。

公开(公告)号：US09030030B2

公开(公告)日：2015-05-12

申请号：US13760187

申请日：2013-02-06

Applicant: STATS ChipPAC, Ltd.

Inventor： KyungHoon Lee ,  KiYoun Jang ,  JoonDong Kim

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L21/50 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/50 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device has a flipchip or PoP semiconductor die mounted to a die attach area interior to a substrate. The substrate has a contact pad area around the die attach area and flow control area between the die attach area and contact pad area. A first channel is formed in a surface of the substrate within the flow control area. The first channel extends around a periphery of the die attach area. A first dam material is formed adjacent to the first channel within the flow control area. An underfill material is deposited between the die and substrate. The first channel and first dam material control outward flow of the underfill material to prevent excess underfill material from covering the contact pad area. A second channel can be formed adjacent to the first dam material. A second dam material can be formed adjacent to the first channel.

Abstract translation: 半导体器件具有安装到衬底内部的管芯附着区域的倒装芯片或PoP半导体管芯。 基板在芯片附着区域周围具有接触焊盘区域以及管芯附着区域和接触焊盘区域之间的流动控制区域。 第一通道形成在流动控制区域内的基板的表面中。 第一通道围绕芯片附接区域的周边延伸。 在流动控制区域内与第一通道相邻地形成第一坝材料。 在模具和衬底之间沉积底部填充材料。 第一通道和第一坝材料控制底部填充材料的向外流动，以防止多余的底部填充材料覆盖接触垫区域。 可以与第一坝材料相邻地形成第二通道。 可以在第一通道附近形成第二坝材料。

公开(公告)号：US20140103503A1

公开(公告)日：2014-04-17

申请号：US14138382

申请日：2013-12-23

Applicant: STATS ChipPAC, Ltd.

Inventor： JaeHyun Lee ,  KiYoun Jang ,  KyungHoon Lee ,  TaeWoo Lee

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49816 ,  H01L21/4814 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76838 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5329 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A semiconductor device has a substrate and first conductive layer formed over the substrate. An insulating layer is formed over the first substrate with an opening over the first conductive layer. A second conductive layer is formed within the opening of the insulating layer. A portion of the second conductive layer is removed to expose a horizontal surface and side surfaces of the second conductive layer below a surface of the insulating layer. The second conductive layer has non-linear surfaces to extend a contact area of the second conductive layer. The horizontal surface and side surfaces can be stepped surfaces or formed as a ring. A third conductive layer is formed over the second conductive layer. A plurality of bumps is formed over the horizontal surface and side surfaces of the second conductive layer. A semiconductor die is mounted to the substrate.

Abstract translation: 半导体器件具有衬底和形成在衬底上的第一导电层。 绝缘层在第一基板的上方形成有第一导电层上的开口。 第二导电层形成在绝缘层的开口内。 去除第二导电层的一部分以暴露第二导电层在绝缘层的表面下方的水平表面和侧表面。 第二导电层具有非线性表面以延伸第二导电层的接触面积。 水平表面和侧表面可以是台阶表面或形成为环形。 在第二导电层上形成第三导电层。 在第二导电层的水平表面和侧表面上形成多个凸块。 将半导体管芯安装到基板上。

公开(公告)号：US08519536B2

公开(公告)日：2013-08-27

申请号：US13691427

申请日：2012-11-30

Applicant: STATS ChipPAC, Ltd.

Inventor： KiYoun Jang ,  DaeSik Choi ,  OhHan Kim ,  DongSoo Moon

IPC: H01L23/48

CPC classification number: H01L21/4853 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device that has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer.

Abstract translation: 一种具有倒装芯片半导体管芯和衬底的半导体器件。 在衬底上形成第一绝缘层。 通过第一绝缘层形成通孔。 导电材料沉积在通孔中以形成导电柱或堆叠的柱状凸块。 导电柱与衬底内的导电层电连接。 在第一绝缘层上形成第二绝缘层。 凸起材料形成在导电柱上。 凸块材料被回流以形成凸块。 去除第一和第二绝缘层。 半导体管芯通过将凸块回流到管芯的导电层而安装到衬底上。 半导体管芯还具有形成在导电层上的第三绝缘层和形成在第一导电层和第三绝缘层上的管芯和UBM的有源表面。

公开(公告)号：US20130175701A1

公开(公告)日：2013-07-11

申请号：US13720516

申请日：2012-12-19

Applicant: STATS ChipPAC, Ltd.

Inventor： SeongWon Park ,  KiYoun Jang ,  KyungHoon Lee ,  JaeHyun Lee

IPC: H01L21/66 ,  H01L23/31

CPC classification number: H01L22/12 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/31 ,  H01L23/3128 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor die. An interconnect structure is formed over an active surface of the semiconductor die. An encapsulant is formed over the semiconductor die and interconnect structure including a first surface opposite the interconnect structure. A peripheral portion of the first surface includes a first roughness disposed outside a footprint of the semiconductor die. A semiconductor die portion of the first surface includes a second roughness less than the first roughness disposed over the footprint of the semiconductor die. The first surface of the encapsulant is disposed within a mold and around the semiconductor die to contact a surface of the mold that includes a third roughness equal to the first roughness and a fourth roughness equal to the second roughness. The first roughness includes a roughness of less than 1.0 micrometers. The second roughness includes a roughness in a range of 1.2-1.8 micrometers.

Abstract translation: 半导体器件包括半导体管芯。 在半导体管芯的有源表面上形成互连结构。 在半导体管芯和互连结构之上形成密封剂，其包括与互连结构相对的第一表面。 第一表面的周边部分包括设置在半导体管芯的占位面外的第一粗糙度。 第一表面的半导体管芯部分包括小于半导体管芯的覆盖区上的第一粗糙度的第二粗糙度。 密封剂的第一表面设置在模具内并且围绕半导体管芯接触模具的表面，该表面包括等于第一粗糙度的第三粗糙度和等于第二粗糙度的第四粗糙度。 第一粗糙度包括小于1.0微米的粗糙度。 第二粗糙度包括在1.2-1.8微米范围内的粗糙度。

公开(公告)号：US20130234324A1

公开(公告)日：2013-09-12

申请号：US13870928

申请日：2013-04-25

Applicant: STATS CHIPPAC, LTD.

Inventor： SungWon Cho ,  KiYoun Jang ,  YongHee Kang ,  Hyung Sang Park

IPC: H01L23/00

CPC classification number: H01L24/09 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1155 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11903 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48158 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81011 ,  H01L2224/81022 ,  H01L2224/81024 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/8385 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/01014 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device.

Abstract translation: 半导体器件具有形成在第一衬底上的第一衬底和第一导电柱。 第二导电柱形成在第一基板上，与第一导电柱交替。 第二导电柱相对于第一导电柱垂直偏移。 第一BOT互连位点形成在第二基底上。 第二BOT互连位置形成在第二衬底上与第一互连位置交替。 第二互连站点相对于第一互连站点垂直偏移。 第一衬底安装到第二衬底，使得第一导电柱与第一互连位置对准并电连接，并且第二导电柱与第二互连位置对准并电连接到第二互连位置。 底部填充材料沉积在第一和第二基底之间。 第一基板可以是倒装芯片型半导体器件。

公开(公告)号：US20140159236A1

公开(公告)日：2014-06-12

申请号：US14181429

申请日：2014-02-14

Applicant: STATS ChipPAC, Ltd.

Inventor： BaeYong Kim ,  KiYoun Jang ,  JoonDong Kim

IPC: H01L23/00

CPC classification number: H01L24/11 ,  C23F11/149 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014

Abstract: An interconnect structure for a semiconductor device is made by forming a contact pad on a substrate, forming an under bump metallization layer over the contact pad, forming a photoresist layer over the substrate, removing a portion of the photoresist layer to form an opening which exposes the UBM, depositing a first conductive material into the opening of the photoresist, removing the photoresist layer, depositing a second conductive material over the first conductive material, and coating the second conductive material with an organic solderability preservative. The interconnect structure is formed without solder reflow. The first conductive layer is nickel and the second conductive layer is copper. The organic solderability preservative is made with benzotriazole, rosin, rosin esters, benzimidazole compounds, or imidazole compounds. The interconnect structure decreases the pitch between the core pillars in the interconnect array and increases the density of I/O contacts on the semiconductor device.

Abstract translation: 半导体器件的互连结构通过在衬底上形成接触焊盘，在接触焊盘上形成凸起下金属化层，在衬底上形成光致抗蚀剂层，去除光致抗蚀剂层的一部分以形成露出的开口 UBM，将第一导电材料沉积到光致抗蚀剂的开口中，去除光致抗蚀剂层，在第一导电材料上沉积第二导电材料，以及用有机可焊性防腐剂涂覆第二导电材料。 互连结构形成，无需焊锡回流。 第一导电层是镍，第二导电层是铜。 有机可焊性防腐剂由苯并三唑，松香，松香酯，苯并咪唑化合物或咪唑化合物制成。 互连结构减小了互连阵列中的芯柱之间的间距，并且增加了半导体器件上的I / O触点的密度。

公开(公告)号：US08742566B2

公开(公告)日：2014-06-03

申请号：US13727116

申请日：2012-12-26

Applicant: STATS ChipPAC, Ltd.

Inventor： KiYoun Jang ,  SungSoo Kim ,  YongHee Kang

IPC: H01L23/04

CPC classification number: H01L23/49811 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/06 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/0401 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/108 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/097 ,  H05K2201/09736 ,  H05K2203/049 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer.

Abstract translation: 半导体器件包括衬底，嵌入并凹入到衬底的第一表面中的第一凹陷导电层和设置在第一表面上方的第一凸起导电层。 在第一凹陷导电层的上表面和第一凸起导电层的上表面之间存在第一垂直偏移。 该器件包括嵌入并凹入到衬底的第二表面中的第二凹陷导电层。 基板的第二表面与第一表面相对。 该装置包括设置在第二表面下方的第二凸起导电层和设置在第一凹入和凸起导电层上的互连结构和第二凹入和凸起导电层。 在第二凹陷导电层的下表面和第二凹陷导电层的下表面之间存在第二垂直偏移。

公开(公告)号：US20130264705A1

公开(公告)日：2013-10-10

申请号：US13906844

申请日：2013-05-31

Applicant: STATS ChipPAC, Ltd.

Inventor： KiYoun Jang ,  DaeSik Choi ,  OhHan Kim ,  DongSoo Moon

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4853 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device that has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer.

Abstract translation: 一种具有倒装芯片半导体管芯和衬底的半导体器件。 在衬底上形成第一绝缘层。 通过第一绝缘层形成通孔。 导电材料沉积在通孔中以形成导电柱或堆叠的柱状凸块。 导电柱与衬底内的导电层电连接。 在第一绝缘层上形成第二绝缘层。 凸起材料形成在导电柱上。 凸块材料被回流以形成凸块。 去除第一和第二绝缘层。 半导体管芯通过将凸块回流到管芯的导电层而安装到衬底上。 半导体管芯还具有形成在导电层上的第三绝缘层和形成在第一导电层和第三绝缘层上的管芯和UBM的有源表面。