公开(公告)号：US09524958B2

公开(公告)日：2016-12-20

申请号：US13928862

申请日：2013-06-27

申请人： STATS ChipPAC, Ltd.

发明人： JoonYoung Choi ,  YongHee Kang ,  HunTeak Lee ,  KeonTaek Kang ,  YoungChul Kim

IPC分类号： H01L21/76 ,  H01L29/24 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L25/50 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device includes a carrier with an interface layer applied over the carrier. The interface layer can include non-conductive paste or non-conductive film. A plurality of semiconductor die is mounted to the carrier and interface layer by pressing the semiconductor die to the carrier and interface layer for one second or less, and simultaneously thermal compression bonding multiple semiconductor die to the carrier and interface layer for 5-10 seconds. By pressing the semiconductor die to the interface layer for a short period of time and then simultaneously thermal compression bonding multiple semiconductor die to the interface layer for a second longer period of time, the overall throughput of die bonding increases to process more die per unit of time. An encapsulant is deposited over the semiconductor die. The carrier is removed and interconnect structure is formed over the semiconductor die and encapsulant.

摘要翻译： 半导体器件包括具有施加在载体上的界面层的载体。 界面层可以包括非导电浆料或非导电膜。 将多个半导体管芯通过将半导体管芯压入载体和界面层1秒以下，同时将多个半导体管芯与载体和界面层热粘合5-10秒，从而安装在载体和界面层上。 通过将半导体管芯压入界面层一段较短的时间，然后同时将多个半导体管芯同时热压粘合到界面层上较长的时间段，芯片接合的总体生产量增加，以处理更多的单位 时间。 密封剂沉积在半导体管芯上。 移除载体并且在半导体管芯和密封剂上形成互连结构。

公开(公告)号：US20150001703A1

公开(公告)日：2015-01-01

申请号：US13928862

申请日：2013-06-27

申请人： STATS ChipPAC, Ltd.

发明人： JoonYoung Choi ,  YongHee Kang ,  HunTeak Lee ,  KeonTaek Kang ,  YoungChul Kim

IPC分类号： H01L25/00 ,  H01L25/065

CPC分类号： H01L25/50 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device includes a carrier with an interface layer applied over the carrier. The interface layer can include non-conductive paste or non-conductive film. A plurality of semiconductor die is mounted to the carrier and interface layer by pressing the semiconductor die to the carrier and interface layer for one second or less, and simultaneously thermal compression bonding multiple semiconductor die to the carrier and interface layer for 5-10 seconds. By pressing the semiconductor die to the interface layer for a short period of time and then simultaneously thermal compression bonding multiple semiconductor die to the interface layer for a second longer period of time, the overall throughput of die bonding increases to process more die per unit of time. An encapsulant is deposited over the semiconductor die. The carrier is removed and interconnect structure is formed over the semiconductor die and encapsulant.

摘要翻译： 半导体器件包括具有施加在载体上的界面层的载体。 界面层可以包括非导电浆料或非导电膜。 将多个半导体管芯通过将半导体管芯压入载体和界面层1秒以下，同时将多个半导体管芯与载体和界面层热粘合5-10秒，从而安装在载体和界面层上。 通过将半导体管芯压入界面层一段较短的时间，然后同时将多个半导体管芯同时热压粘合到界面层上较长的时间段，芯片接合的总体生产量增加，以处理更多的单位 时间。 密封剂沉积在半导体管芯上。 移除载体并且在半导体管芯和密封剂上形成互连结构。

公开(公告)号：US08742566B2

公开(公告)日：2014-06-03

申请号：US13727116

申请日：2012-12-26

申请人： STATS ChipPAC, Ltd.

发明人： KiYoun Jang ,  SungSoo Kim ,  YongHee Kang

IPC分类号： H01L23/04

CPC分类号： H01L23/49811 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/06 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/0401 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/108 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/097 ,  H05K2201/09736 ,  H05K2203/049 ,  H05K2203/1476 ,  H01L2924/00

摘要： A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer.

摘要翻译： 半导体器件包括衬底，嵌入并凹入到衬底的第一表面中的第一凹陷导电层和设置在第一表面上方的第一凸起导电层。 在第一凹陷导电层的上表面和第一凸起导电层的上表面之间存在第一垂直偏移。 该器件包括嵌入并凹入到衬底的第二表面中的第二凹陷导电层。 基板的第二表面与第一表面相对。 该装置包括设置在第二表面下方的第二凸起导电层和设置在第一凹入和凸起导电层上的互连结构和第二凹入和凸起导电层。 在第二凹陷导电层的下表面和第二凹陷导电层的下表面之间存在第二垂直偏移。

公开(公告)号：US08896133B2

公开(公告)日：2014-11-25

申请号：US13870928

申请日：2013-04-25

申请人： STATS ChipPAC, Ltd.

发明人： SungWon Cho ,  KiYoun Jang ,  YongHee Kang ,  Hyung Sang Park

IPC分类号： H01L23/48 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56

CPC分类号： H01L24/09 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1155 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11903 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48158 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81011 ,  H01L2224/81022 ,  H01L2224/81024 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/8385 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/01014 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device.

摘要翻译： 半导体器件具有形成在第一衬底上的第一衬底和第一导电柱。 第二导电柱形成在第一基板上，与第一导电柱交替。 第二导电柱相对于第一导电柱垂直偏移。 第一BOT互连位点形成在第二基底上。 第二BOT互连位置形成在第二衬底上与第一互连位置交替。 第二互连站点相对于第一互连站点垂直偏移。 第一衬底安装到第二衬底，使得第一导电柱与第一互连位置对准并电连接，并且第二导电柱与第二互连位置对准并电连接到第二互连位置。 底部填充材料沉积在第一和第二基底之间。 第一基板可以是倒装芯片型半导体器件。

公开(公告)号：US20130134586A1

公开(公告)日：2013-05-30

申请号：US13727116

申请日：2012-12-26

申请人： STATS ChipPAC, Ltd.

发明人： KiYoun Jang ,  SungSoo Kim ,  YongHee Kang

IPC分类号： H01L23/498

CPC分类号： H01L23/49811 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/06 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/0401 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/108 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/097 ,  H05K2201/09736 ,  H05K2203/049 ,  H05K2203/1476 ,  H01L2924/00

摘要： A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer.

摘要翻译： 半导体器件包括衬底，嵌入并凹入到衬底的第一表面中的第一凹陷导电层和设置在第一表面上方的第一凸起导电层。 在第一凹陷导电层的上表面和第一凸起导电层的上表面之间存在第一垂直偏移。 该器件包括嵌入并凹入到衬底的第二表面中的第二凹陷导电层。 基板的第二表面与第一表面相对。 该装置包括设置在第二表面下方的第二凸起导电层和设置在第一凹入和凸起导电层上的互连结构和第二凹入和凸起导电层。 在第二凹陷导电层的下表面和第二凹陷导电层的下表面之间存在第二垂直偏移。

公开(公告)号：US20130234324A1

公开(公告)日：2013-09-12

申请号：US13870928

申请日：2013-04-25

申请人： STATS CHIPPAC, LTD.

发明人： SungWon Cho ,  KiYoun Jang ,  YongHee Kang ,  Hyung Sang Park

IPC分类号： H01L23/00

CPC分类号： H01L24/09 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1155 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11903 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48158 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81011 ,  H01L2224/81022 ,  H01L2224/81024 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/8385 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/01014 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device.

摘要翻译： 半导体器件具有形成在第一衬底上的第一衬底和第一导电柱。 第二导电柱形成在第一基板上，与第一导电柱交替。 第二导电柱相对于第一导电柱垂直偏移。 第一BOT互连位点形成在第二基底上。 第二BOT互连位置形成在第二衬底上与第一互连位置交替。 第二互连站点相对于第一互连站点垂直偏移。 第一衬底安装到第二衬底，使得第一导电柱与第一互连位置对准并电连接，并且第二导电柱与第二互连位置对准并电连接到第二互连位置。 底部填充材料沉积在第一和第二基底之间。 第一基板可以是倒装芯片型半导体器件。