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    Semiconductor device and method of controlling warpage in reconstituted wafer
    1.
    发明授权
    Semiconductor device and method of controlling warpage in reconstituted wafer 有权

    公开(公告)号：US10297556B2

    公开(公告)日：2019-05-21

    申请号：US15415686

    申请日：2017-01-25

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Kian Meng Heng ,  Hin Hwa Goh ,  Jose Alvin Caparas ,  Kang Chen ,  Seng Guan Chow ,  Yaojian Lin

    IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

    Abstract: A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced.

    Semiconductor device and method to minimize stress on stack via
    2.
    发明授权
    Semiconductor device and method to minimize stress on stack via 有权

    公开(公告)号：US10804153B2

    公开(公告)日：2020-10-13

    申请号：US15169095

    申请日：2016-05-31

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Yaojian Lin ,  Seng Guan Chow

    IPC: H01L21/78 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/31 ,  H01L21/66 ,  H01L21/56

    Abstract: A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die. A first via is formed in the first insulating layer over a contact pad of the semiconductor die. A first conductive layer is disposed over the first insulating layer and in the first via. A second insulating layer is disposed over a portion of the first insulating layer and first conductive layer. An island of the second insulating layer is formed over the first conductive layer and within the first via. The first conductive layer adjacent to the island is devoid of the second insulating layer. A second conductive layer is disposed over the first conductive layer, second insulating layer, and island. The second conductive layer has a corrugated structure. A width of the island is greater than a width of the first via.

    Semiconductor Device and Method to Minimize Stress on Stack Via
    3.
    发明申请
    Semiconductor Device and Method to Minimize Stress on Stack Via 审中-公开
    半导体器件和方法，以最大限度地减少堆叠的应力

    公开(公告)号：US20160276237A1

    公开(公告)日：2016-09-22

    申请号：US15169095

    申请日：2016-05-31

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Yaojian Lin ,  Seng Guan Chow

    IPC: H01L23/31 ,  H01L21/78 ,  H01L23/522 ,  H01L21/66 ,  H01L21/768 ,  H01L23/00

    Abstract: A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die. A first via is formed in the first insulating layer over a contact pad of the semiconductor die. A first conductive layer is disposed over the first insulating layer and in the first via. A second insulating layer is disposed over a portion of the first insulating layer and first conductive layer. An island of the second insulating layer is formed over the first conductive layer and within the first via. The first conductive layer adjacent to the island is devoid of the second insulating layer. A second conductive layer is disposed over the first conductive layer, second insulating layer, and island. The second conductive layer has a corrugated structure. A width of the island is greater than a width of the first via.

    Abstract translation: 半导体器件具有半导体管芯。 第一绝缘层设置在半导体管芯上。 在半导体管芯的接触焊盘上的第一绝缘层中形成第一通孔。 第一导电层设置在第一绝缘层上和第一通孔中。 第二绝缘层设置在第一绝缘层和第一导电层的一部分上。 第二绝缘层的岛形成在第一导电层之上并在第一通孔内。 与岛相邻的第一导电层没有第二绝缘层。 第二导电层设置在第一导电层，第二绝缘层和岛上。 第二导电层具有波纹结构。 岛的宽度大于第一通孔的宽度。

    Semiconductor device and method of controlling warpage in reconstituted wafer
    4.
    发明授权
    Semiconductor device and method of controlling warpage in reconstituted wafer 有权

    公开(公告)号：US10163747B2

    公开(公告)日：2018-12-25

    申请号：US15461713

    申请日：2017-03-17

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Kian Meng Heng ,  Hin Hwa Goh ,  Jose Alvin Caparas ,  Kang Chen ,  Seng Guan Chow ,  Yaojian Lin

    IPC: H01L21/56 ,  H01L23/31 ,  H01L21/78 ,  H01L23/00

    Abstract: A semiconductor device has a substrate with a plurality of active semiconductor die disposed over a first portion of the substrate and a plurality of non-functional semiconductor die disposed over a second portion of the substrate while leaving a predetermined area of the substrate devoid of the active semiconductor die and non-functional semiconductor die. The predetermined area of the substrate devoid of the active semiconductor die and non-functional semiconductor die includes a central area, checkerboard pattern, linear, or diagonal area of the substrate. The substrate can be a circular shape or rectangular shape. An encapsulant is deposited over the active semiconductor die, non-functional semiconductor die, and substrate. An interconnect structure is formed over the semiconductor die. The absence of active semiconductor die and non-functional semiconductor die from the predetermined areas of the substrate reduces bending stress in that area of the substrate.

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