公开(公告)号：US20140291782A1

公开(公告)日：2014-10-02

申请号：US13853645

申请日：2013-03-29

Applicant: STMICROELECTRONICS PTE LTD.

Inventor： Kim-Yong Goh ,  Yiyi Ma ,  Wei Zhen Goh

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81B7/0058 ,  B81C2203/0109 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/00014

Abstract: Methods and devices for packaging integrated circuits. A packaged device may include an integrated circuit, a first packaging component including a patterned surface, and a second packaging component. The patterned surface of the first packaging component may be adhesively coupled to a surface of the second packaging component or a surface of the integrated circuit. The integrated circuit may be at least partially enclosed between the first and second packaging components. A packaging method may include patterning a surface of a packaging component of an integrated circuit package. The surface of the packaging component may be for adhesively coupling to a second component to at least partially enclose an integrated circuit in the integrated circuit package.

Abstract translation: 集成电路封装的方法和装置。 封装的装置可以包括集成电路，包括图案化表面的第一包装部件和第二包装部件。 第一包装部件的图案化表面可以粘合地耦合到第二包装部件的表面或集成电路的表面。 集成电路可以至少部分地封装在第一和第二封装部件之间。 包装方法可以包括图案化集成电路封装的封装部件的表面。 包装部件的表面可以用于粘合地耦合到第二部件以至少部分地封装集成电路封装中的集成电路。

公开(公告)号：US09824924B2

公开(公告)日：2017-11-21

申请号：US13853856

申请日：2013-03-29

Applicant: STMicroelectronics Pte Ltd.

Inventor： Kim-Yong Goh ,  Xueren Zhang ,  Yiyi Ma

IPC: H01L23/02 ,  H01L21/78 ,  H01L23/00 ,  B81B7/00 ,  H01L23/053

CPC classification number: H01L21/78 ,  B81B7/0048 ,  H01L23/053 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/29198 ,  H01L2224/32058 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/83007 ,  H01L2924/00014 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/12042 ,  H01L2924/16151 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.

公开(公告)号：US10658238B2

公开(公告)日：2020-05-19

申请号：US15784764

申请日：2017-10-16

Applicant: STMicroelectronics Pte Ltd

Inventor： Kim-Yong Goh ,  Xueren Zhang ,  Yiyi Ma

IPC: B81B7/00 ,  H01L21/78 ,  H01L23/00 ,  H01L27/146 ,  H01L23/053

Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.

公开(公告)号：US20150084171A1

公开(公告)日：2015-03-26

申请号：US14034121

申请日：2013-09-23

Applicant: STMicroelectronics Pte. Ltd.

Inventor： Yiyi Ma ,  Kim-Yong Goh ,  Xueren Zhang

IPC: H01L23/495

CPC classification number: H01L21/4832 ,  H01L21/486 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24101 ,  H01L2224/24247 ,  H01L2224/25171 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82106 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A non-lead (QFN) semiconductor package is disclosed. The package includes a die attach pad and a semiconductor die supported by the die attached pad. The semiconductor die includes a plurality of pads on an active surface thereof. The package further includes a plurality of terminal leads, an encapsulant that encapsulates the semiconductor die, and a redistribution layer including a plurality of interconnections electrically connecting the pads to the terminal leads. A method of making the package is also disclosed.

Abstract translation: 公开了一种非引线（QFN）半导体封装。 封装包括管芯附接焊盘和由管芯附接焊盘支撑的半导体管芯。 半导体管芯包括在其有效表面上的多个焊盘。 该封装还包括多个端子引线，封装半导体管芯的密封剂，以及包括将焊盘电连接到端子引线的多个互连的再分配层。 还公开了制造包装的方法。

公开(公告)号：US20180040514A1

公开(公告)日：2018-02-08

申请号：US15784764

申请日：2017-10-16

Applicant: STMicroelectronics Pte Ltd

Inventor： Kim-Yong Goh ,  Xueren Zhang ,  Yiyi Ma

IPC: H01L21/78

CPC classification number: H01L21/78 ,  B81B7/0048 ,  H01L23/053 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L27/14618 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/29198 ,  H01L2224/32058 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/83007 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/12042 ,  H01L2924/16151 ,  H01L2924/014

Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.

公开(公告)号：US09576912B1

公开(公告)日：2017-02-21

申请号：US14957865

申请日：2015-12-03

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yiyi Ma ,  Kim-Yong Goh ,  Xueren Zhang

IPC: H01L23/12 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0391 ,  H01L2224/05008 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2224/023 ,  H01L2924/07025

Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor substrate, a back end of line (BEOL) layer on the semiconductor substrate and having a peripheral edge recessed inwardly from an adjacent peripheral edge of the semiconductor substrate. A first dielectric layer is over the BEOL layer and wraps around the peripheral edge of the BEOL layer. A redistribution layer is over the first dielectric layer and a second dielectric layer is over the redistribution layer.

Abstract translation: 晶片级芯片级封装（WLCSP）包括半导体衬底，半导体衬底上的后端（BEOL）层，并且具有从半导体衬底的相邻外围边缘向内凹陷的外围边缘。 第一电介质层在BEOL层上方并且缠绕在BEOL层的外围边缘周围。 再分布层在第一介电层上方，第二介电层位于再分布层上。

公开(公告)号：US09379034B1

公开(公告)日：2016-06-28

申请号：US14585566

申请日：2014-12-30

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Kim-Yong Goh ,  Yiyi Ma ,  Xueren Zhang

IPC: H01L23/10 ,  H01L23/31 ,  H01L23/498 ,  H01L23/367 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/3135 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of making an electronic device may include positioning an integrated circuit (IC) die on an upper surface of a grid array substrate having connections on a lower surface thereof and coupling respective bond pads of the IC die to the grid array with bond wires. The method may also include forming a first encapsulating layer over the IC die and bond wires and positioning a heat spreader on the substrate above the first encapsulating layer after forming the first encapsulating layer. The method may further include forming a second encapsulating layer over the first encapsulating layer and embedding the heat spreader in the second encapsulating layer.

Abstract translation: 制造电子设备的方法可以包括将集成电路（IC）管芯定位在具有在其下表面上的连接的栅格阵列衬底的上表面上，并且将IC芯片的各个接合焊盘与接合线耦合到栅极阵列。 该方法还可以包括在IC芯片上方形成第一封装层，并且在形成第一封装层之后，将第一封装层上的基板上的散热器定位在第一封装层上方的基板上。 该方法还可以包括在第一封装层上形成第二封装层，并将散热器嵌入第二封装层中。

公开(公告)号：US09679870B2

公开(公告)日：2017-06-13

申请号：US14565484

申请日：2014-12-10

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yiyi Ma ,  Kim-Yong Goh ,  Xueren Zhang ,  Wei Zhen Goh

IPC: H01L23/00 ,  H01L23/482 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L24/85 ,  H01L23/3107 ,  H01L23/4822 ,  H01L23/49555 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48177 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit (IC) device includes an IC and encapsulating material surrounding the IC. Leads are coupled to the IC and extend outwardly from sides of the encapsulating material, with each lead having three contiguous exposed segments with upper and lower bends defining a Z-shape. In another example, the leads include an upper horizontal segment, lower horizontal segment, and intermediate curved segment extending upwardly from the upper horizontal segment and downwardly to the lower horizontal segment.

公开(公告)号：US20160190029A1

公开(公告)日：2016-06-30

申请号：US14585566

申请日：2014-12-30

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Kim-Yong GOH ,  Yiyi Ma ,  Xueren Zhang

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/367

CPC classification number: H01L23/3135 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of making an electronic device may include positioning an integrated circuit (IC) die on an upper surface of a grid array substrate having connections on a lower surface thereof and coupling respective bond pads of the IC die to the grid array with bond wires. The method may also include forming a first encapsulating layer over the IC die and bond wires and positioning a heat spreader on the substrate above the first encapsulating layer after forming the first encapsulating layer. The method may further include forming a second encapsulating layer over the first encapsulating layer and embedding the heat spreader in the second encapsulating layer.

Abstract translation: 制造电子设备的方法可以包括将集成电路（IC）裸片定位在具有在其下表面上的连接的网格阵列基板的上表面上，并且将IC芯片的各个接合焊盘与接合线连接到网格阵列。 该方法还可以包括在IC芯片上方形成第一封装层，并且在形成第一封装层之后，将第一封装层上的基板上的散热器定位在第一封装层上方的基板上。 该方法还可以包括在第一封装层上形成第二封装层，并将散热器嵌入第二封装层中。

公开(公告)号：US08907465B2

公开(公告)日：2014-12-09

申请号：US13853645

申请日：2013-03-29

Applicant: STMicroelectronics Pte Ltd.

Inventor： Kim-Yong Goh ,  Yiyi Ma ,  Wei Zhen Goh

IPC: H01L23/02 ,  B81C1/00 ,  B81B7/00

CPC classification number: B81B7/0058 ,  B81C2203/0109 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/00014

Abstract: Methods and devices for packaging integrated circuits. A packaged device may include an integrated circuit, a first packaging component including a patterned surface, and a second packaging component. The patterned surface of the first packaging component may be adhesively coupled to a surface of the second packaging component or a surface of the integrated circuit. The integrated circuit may be at least partially enclosed between the first and second packaging components. A packaging method may include patterning a surface of a packaging component of an integrated circuit package. The surface of the packaging component may be for adhesively coupling to a second component to at least partially enclose an integrated circuit in the integrated circuit package.

Abstract translation: 集成电路封装的方法和装置。 封装的装置可以包括集成电路，包括图案化表面的第一包装部件和第二包装部件。 第一包装部件的图案化表面可以粘合地耦合到第二包装部件的表面或集成电路的表面。 集成电路可以至少部分地封装在第一和第二封装部件之间。 包装方法可以包括图案化集成电路封装的封装部件的表面。 包装部件的表面可以用于粘合地耦合到第二部件以至少部分地封装集成电路封装中的集成电路。