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1.发明申请公开(公告)号：US20180279478A1
公开(公告)日：2018-09-27
申请号：US15993107
申请日：2018-05-30
Applicant: Samsung Electro-Mechanics Co., Ltd.
Inventor： Seung Eun LEE , Yee Na SHIN , Yul Kyo CHUNG , Doo Hwan LEE
CPC classification number: H05K1/185 , H01L21/568 , H01L2224/04105 , H01L2224/2518 , H01L2224/8203 , H01L2924/3512 , H05K3/4644 , H05K3/4697 , H05K2201/10015 , H05K2203/1469 , Y10T29/4913
Abstract: Disclosed herein is a printed circuit board (PCB) including an embedded electronic component, including: a core having a cavity; an electronic component inserted into the cavity having a rough surface formed on surfaces of external electrodes provided on both lateral portions thereof, a low rough surface being formed in a portion of the rough surfaces; insulating layers laminated on upper and lower portions of the core and bonded to an outer circumferential surface of the electronic component insertedly positioned in the cavity; and an external circuit pattern provided on the insulating layers.
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2.发明申请公开(公告)号：US20140321084A1
公开(公告)日：2014-10-30
申请号：US14061047
申请日：2013-10-23
Applicant: Samsung Electro-Mechanics Co., Ltd.
Inventor： Seung Eun LEE , Yul Kyo CHUNG , Yee Na SHIN , Doo Hwan LEE
CPC classification number: H05K1/185 , H01L21/568 , H01L24/19 , H01L24/20 , H01L2224/04105 , H01L2924/12042 , H01L2924/3511 , H05K3/4602 , H05K2201/09854 , H05K2201/10636 , H05K2203/1469 , Y02P70/611 , Y10T29/49139 , H01L2924/00
Abstract: Disclosed herein are a printed circuit board including an electronic component embedded therein and a method for manufacturing the same. The printed circuit board including an electronic component embedded therein includes: a core formed with a cavity which is formed of a through hole and has a side wall formed with an inclined surface having a top and bottom symmetrically formed based on a central portion thereof; an electronic component embedded in the cavity; insulating layers stacked on upper and lower portions of the core including the electronic component; and external circuit layers formed on the insulating layers.
Abstract translation: 这里公开了包括嵌入其中的电子部件的印刷电路板及其制造方法。 包括嵌入其中的电子部件的印刷电路板包括：芯，其形成有由通孔形成的空腔，并且具有形成有基于其中心部分对称地形成有顶部和底部的倾斜表面的侧壁; 嵌入腔内的电子部件; 堆叠在包括电子部件的芯的上部和下部的绝缘层; 以及形成在绝缘层上的外部电路层。
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公开(公告)号：US20150380276A1
公开(公告)日：2015-12-31
申请号：US14848726
申请日：2015-09-09
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Yee Na SHIN , Young Nam HWANG , Hyun Bok KWON , Seung Wan WOO
IPC: H01L21/56 , H01L21/288 , H01L21/768 , H01L21/78 , H01L23/00
CPC classification number: H01L21/561 , H01L21/288 , H01L21/565 , H01L21/568 , H01L21/76802 , H01L21/76879 , H01L21/78 , H01L23/3128 , H01L23/481 , H01L23/544 , H01L24/11 , H01L24/19 , H01L24/27 , H01L24/96 , H01L24/97 , H01L2223/54426 , H01L2223/54486 , H01L2224/12105 , H01L2224/14 , H01L2924/12042 , H01L2924/181 , H01L2924/00
Abstract: Disclosed herein is a method for manufacturing a semiconductor package. According to a preferred embodiment of the present invention, a method for manufacturing a semiconductor package includes: preparing a rectangular frame having a plurality of quadrangular holes; attaching a plurality of semiconductor chips and the frame on one surface of a tape; forming a molding part on the tape to cover the semiconductor chip and the frame; peeling the tape; forming a resin layer at a portion at which the tape is peeled; and forming a wiring on the resin layer to be connected to the semiconductor chip.
Abstract translation: 本文公开了一种半导体封装的制造方法。 根据本发明的优选实施例，一种制造半导体封装的方法包括：制备具有多个四边形孔的矩形框架; 将多个半导体芯片和框架附接在磁带的一个表面上; 在所述带上形成模制部件以覆盖所述半导体芯片和所述框架; 剥皮; 在剥离的部分形成树脂层; 并在与半导体芯片连接的树脂层上形成布线。
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公开(公告)号：US20150147849A1
公开(公告)日：2015-05-28
申请号：US14527733
申请日：2014-10-29
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Yee Na SHIN , Young Nam Hwang , Hyun Bok Kwon , Seung Wan Woo
CPC classification number: H01L21/561 , H01L21/288 , H01L21/565 , H01L21/568 , H01L21/76802 , H01L21/76879 , H01L21/78 , H01L23/3128 , H01L23/481 , H01L23/544 , H01L24/11 , H01L24/19 , H01L24/27 , H01L24/96 , H01L24/97 , H01L2223/54426 , H01L2223/54486 , H01L2224/12105 , H01L2224/14 , H01L2924/12042 , H01L2924/181 , H01L2924/00
Abstract: Disclosed herein is a method for manufacturing a semiconductor package. According to a preferred embodiment of the present invention, a method for manufacturing a semiconductor package includes: preparing a rectangular frame having a plurality of quadrangular holes; attaching a plurality of semiconductor chips and the frame on one surface of a tape; forming a molding part on the tape to cover the semiconductor chip and the frame; peeling the tape; forming a resin layer at a portion at which the tape is peeled; and forming a wiring on the resin layer to be connected to the semiconductor chip.0
Abstract translation: 本文公开了一种半导体封装的制造方法。 根据本发明的优选实施例，一种制造半导体封装的方法包括：制备具有多个四边形孔的矩形框架; 将多个半导体芯片和框架附接在磁带的一个表面上; 在所述带上形成模制部件以覆盖所述半导体芯片和所述框架; 剥皮; 在剥离的部分形成树脂层; 并在与半导体芯片连接的树脂层上形成布线
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5.发明申请公开(公告)号：US20140182896A1
公开(公告)日：2014-07-03
申请号：US14143616
申请日：2013-12-30
Applicant: SAMSUNG, ELECTRO-MECHANICS CO., LTD.
Inventor： Doo Hwan LEE , Yul Kyo CHUNG , Dae Hyun PARK , Yee Na SHIN , Seung Eun LEE
CPC classification number: H05K1/185 , H01L2224/16227 , H01L2924/15313 , H05K1/0231 , H05K3/4602 , H05K3/4644 , H05K2201/10015 , Y10T29/49139
Abstract: A substrate having an electronic component embedded therein includes a first insulating layer including a cavity and including first and second circuit patterns provided on upper and lower surfaces thereof, respectively; the electronic component at least partially inserted into the cavity and including an external electrode; a plurality of build-up insulating layers stacked on or beneath the first insulating layer; upper and lower circuit patterns formed on the build-up insulating layers, respectively; and a plurality of vias connecting the external electrode, the upper circuit pattern, the first circuit pattern, the second circuit pattern, and the lower circuit pattern.
Abstract translation: 嵌入其中的电子部件的基板包括：第一绝缘层，包括空腔，并且分别包括设置在其上表面和下表面上的第一和第二电路图案; 所述电子部件至少部分地插入所述腔并包括外部电极; 堆叠在所述第一绝缘层上或下的多个积层绝缘层; 分别形成在积层绝缘层上的上下电路图案; 以及连接外部电极，上部电路图案，第一电路图案，第二电路图案和下部电路图案的多个通孔。
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Patent Agency Ranking
6.发明申请CORE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND SUBSTRATE WITH BUILT-IN ELECTRONIC COMPONENTS AND METHOD FOR MANUFACTURING THE SAME 审中-公开核心基板及其制造方法以及具有内置电子元件的基板及其制造方法公开(公告)号：US20140177192A1
公开(公告)日：2014-06-26
申请号：US14104482
申请日：2013-12-12
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Seung Eun Lee , Yee Na SHIN , Yul Kyo CHUNG , Doo Hwan LEE
CPC classification number: H05K1/185 , H01L2924/3511 , H05K3/4602 , H05K2201/0129 , H05K2201/0195 , H05K2201/10636 , Y02P70/611 , Y10T29/4913 , Y10T428/24942
Abstract: The present invention relates to a core substrate, a manufacturing method thereof, and a substrate with built-in electronic components and a method for manufacturing the same. In accordance with an embodiment of the present invention, a core substrate including: a first insulating layer; and a second insulating layer stacked on upper and lower surfaces of the first insulating layer and made of a material with a glass transition temperature lower than that of the first insulating layer.
Abstract translation: 芯基板及其制造方法以及具有内置电子部件的基板及其制造方法技术领域本发明涉及芯基板及其制造方法以及具有内置电子部件的基板及其制造方法。 根据本发明的实施例，一种芯基板，包括：第一绝缘层; 以及第二绝缘层，其堆叠在所述第一绝缘层的上表面和下表面上，并且由玻璃化转变温度低于所述第一绝缘层的玻璃化转变温度的材料制成。
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公开(公告)号：US20140144676A1
公开(公告)日：2014-05-29
申请号：US14092331
申请日：2013-11-27
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Yul Kyo CHUNG , Doo Hwan LEE , Seung Eun LEE , Yee Na SHIN
CPC classification number: H05K1/186 , H01L2924/15311 , H05K3/4644 , H05K3/4697 , H05K2201/10015 , H05K2201/10636 , Y02P70/611 , Y10T29/4913
Abstract: The present invention relates to an electronic component embedded substrate including: a first insulating layer including a cavity; an electronic component inserted in the cavity; a first metal pattern formed on a lower surface of the first insulating layer to mount the electronic component thereon and including at least one guide hole for exposing a portion of the external electrode; a second insulating layer formed on the lower surface of the first insulating layer to cover the first metal pattern; a first circuit pattern formed on a lower surface of the second insulating layer; and a first via for electrically connecting the first external electrode exposed through the guide hole and the first circuit pattern, and can improve electrical connectivity between the external electrode and the via even when the size of the external electrode of the electronic component is reduced than before.
Abstract translation: 电子部件嵌入式基板技术领域本发明涉及电子部件嵌入式基板，具备：包括空腔的第一绝缘层; 插入腔内的电子部件; 形成在所述第一绝缘层的下表面上以将所述电子部件安装在其上并且包括用于暴露所述外部电极的一部分的至少一个引导孔的第一金属图案; 形成在所述第一绝缘层的下表面上以覆盖所述第一金属图案的第二绝缘层; 形成在所述第二绝缘层的下表面上的第一电路图案; 以及用于电连接通过引导孔暴露的第一外部电极和第一电路图案的第一通孔，并且即使当电子部件的外部电极的尺寸比以前更小时，也可以改善外部电极和通孔之间的电连接性 。
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8.发明申请PASSIVE DEVICE EMBEDDED IN SUBSTRATE AND SUBSTRATE WITH PASSIVE DEVICE EMBEDDED THEREIN 有权被埋入衬底的被动器件和嵌入式器件的被动器件公开(公告)号：US20140090881A1
公开(公告)日：2014-04-03
申请号：US14041235
申请日：2013-09-30
Applicant: Samsung Electro-Mechanics Co., Ltd.
Inventor： Yee Na SHIN , Yul Kyo Chung , Seung Eun Lee
IPC: H05K1/18
CPC classification number: H05K1/185 , H05K3/4682 , H05K2203/308
Abstract: The present invention relates to a passive device embedded in a substrate, which includes a laminate formed by alternately laminating a plurality of internal electrodes and dielectric layers; a first external electrode covering one side surface of the laminate and having a first upper cover region, which covers a part of an upper portion of the laminate, and a first lower cover region, which covers a part of a lower portion of the laminate and is smaller than the first upper cover region; and a second external electrode covering the other side surface of the laminate and having a second lower cover region, which covers a part of the lower portion of the laminate, and a second upper cover region, which covers a part of the upper portion of the laminate and is smaller than the second lower cover region, and the substrate.
Abstract translation: 本发明涉及嵌入基板中的无源器件，其包括通过交替层叠多个内部电极和电介质层而形成的层压体; 覆盖所述层压体的一个侧面的第一外部电极，具有覆盖所述层叠体的上部的一部分的第一上盖区域和覆盖所述层压体的下部的一部分的第一下盖区域，以及 小于第一上盖区域; 以及覆盖所述层叠体的另一侧面的第二外部电极，具有覆盖所述层叠体的下部的一部分的第二下部覆盖区域和覆盖所述层叠体的上部的一部分的第二上部覆盖区域 并且小于第二下盖区域和基板。
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公开(公告)号：US20160205773A1
公开(公告)日：2016-07-14
申请号：US15074209
申请日：2016-03-18
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Doo Hwan LEE , Yul Kyo CHUNG , Yee Na SHIN , Seung Eun LEE
CPC classification number: H05K3/002 , H01L24/19 , H01L24/24 , H01L24/82 , H01L2224/12105 , H01L2224/24227 , H01L2224/73267 , H01L2224/92244 , H01L2924/12042 , H01L2924/15153 , H01L2924/15311 , H01L2924/15788 , H01L2924/3511 , H05K1/0271 , H05K1/0298 , H05K1/0306 , H05K1/115 , H05K1/185 , H05K3/4605 , H05K3/4644 , H05K3/4697 , H05K2201/10015 , H05K2203/1469 , Y10T29/4913 , H01L2924/00
Abstract: A circuit board includes an inorganic material insulating layer, a first circuit pattern layer formed on a surface of the inorganic material insulating layer, a first build-up insulating layer formed on the inorganic material insulating layer and formed of an organic material, and a second circuit pattern layer formed on a surface of the first build-up insulating layer.
Abstract translation: 电路板包括无机材料绝缘层，形成在无机材料绝缘层的表面上的第一电路图案层，形成在无机材料绝缘层上并由有机材料形成的第一累积绝缘层，第二 电路图案层形成在第一堆积绝缘层的表面上。
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公开(公告)号：US20150027757A1
公开(公告)日：2015-01-29
申请号：US14074372
申请日：2013-11-07
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Yee Na SHIN , Seung Eun Lee
CPC classification number: H05K3/4605 , H01L23/15 , H01L23/49827 , H01L23/50 , H01L2924/0002 , H05K1/0271 , H05K1/185 , H05K3/107 , H05K3/426 , H05K3/4661 , H05K2201/0376 , H05K2201/098 , H01L2924/00
Abstract: Disclosed herein is a printed circuit board (PCB) including a glass core for maintaining sufficient rigidity while maintaining a thin thickness to minimize warpage. The PCB includes a glass core having upper and lower surfaces in which pattern formation grooves and through via holes are formed, a plating layer filled in the pattern formation groves and the through via holes, insulating layers stacked on the upper and lower surfaces of the glass core, and solder resist layers formed on the insulating layers via coating.
Abstract translation: 本文公开了一种印刷电路板（PCB），其包括玻璃芯，用于保持足够的刚度，同时保持薄的厚度以使翘曲最小化。 PCB包括具有上表面和下表面的玻璃芯，其中形成图案形成沟槽和穿过通孔，填充在图案形成沟槽中的镀层和穿通通孔，堆叠在玻璃的上表面和下表面上的绝缘层 芯和阻焊层，通过涂层形成在绝缘层上。
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