PRINTED CIRCUIT BOARD
    3.
    发明申请

    公开(公告)号:US20250071902A1

    公开(公告)日:2025-02-27

    申请号:US18625488

    申请日:2024-04-03

    Abstract: The present disclosure relates to a printed circuit board including: a glass layer; a plurality of blind cavities respectively penetrating through a portion of the glass layer from an upper surface or a lower surface of the glass layer; a plurality of passive elements respectively disposed in the plurality of blind cavities; and an insulating layer covering at least a portion of each of the glass layer and the plurality of passive elements and disposed in at least a portion of each of the plurality of blind cavities. At least two of the plurality of blind cavities have different depths.

    PRINTED CIRCUIT BOARD
    4.
    发明申请

    公开(公告)号:US20210410285A1

    公开(公告)日:2021-12-30

    申请号:US17215916

    申请日:2021-03-29

    Abstract: A printed circuit board includes a first insulating layer, a second insulating layer disposed on a lower surface of the first insulating layer, an electronic component embedded in the second insulating layer and at least partially in contact with the first insulating layer, a first wiring layer disposed on an upper surface of the first insulating layer, a second wiring layer disposed on a lower surface of the second insulating layer, and a first wiring via penetrating through the first and second insulating layers and connecting at least portions of the first and second wiring layers to each other.

    SUBSTRATE HAVING ELECTRONIC COMPONENT EMBEDDED THEREIN AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    SUBSTRATE HAVING ELECTRONIC COMPONENT EMBEDDED THEREIN AND METHOD OF MANUFACTURING THE SAME 有权
    具有嵌入式电子元件的基板及其制造方法

    公开(公告)号:US20140182896A1

    公开(公告)日:2014-07-03

    申请号:US14143616

    申请日:2013-12-30

    Abstract: A substrate having an electronic component embedded therein includes a first insulating layer including a cavity and including first and second circuit patterns provided on upper and lower surfaces thereof, respectively; the electronic component at least partially inserted into the cavity and including an external electrode; a plurality of build-up insulating layers stacked on or beneath the first insulating layer; upper and lower circuit patterns formed on the build-up insulating layers, respectively; and a plurality of vias connecting the external electrode, the upper circuit pattern, the first circuit pattern, the second circuit pattern, and the lower circuit pattern.

    Abstract translation: 嵌入其中的电子部件的基板包括:第一绝缘层,包括空腔,并且分别包括设置在其上表面和下表面上的第一和第二电路图案; 所述电子部件至少部分地插入所述腔并包括外部电极; 堆叠在所述第一绝缘层上或下的多个积层绝缘层; 分别形成在积层绝缘层上的上下电路图案; 以及连接外部电极,上部电路图案,第一电路图案,第二电路图案和下部电路图案的多个通孔。

    ELECTRONIC COMPONENT EMBEDDED SUBSTRATE AND MANUFACTURING METHOD THEREOF
    9.
    发明申请
    ELECTRONIC COMPONENT EMBEDDED SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权
    电子元件嵌入式基板及其制造方法

    公开(公告)号:US20140144676A1

    公开(公告)日:2014-05-29

    申请号:US14092331

    申请日:2013-11-27

    Abstract: The present invention relates to an electronic component embedded substrate including: a first insulating layer including a cavity; an electronic component inserted in the cavity; a first metal pattern formed on a lower surface of the first insulating layer to mount the electronic component thereon and including at least one guide hole for exposing a portion of the external electrode; a second insulating layer formed on the lower surface of the first insulating layer to cover the first metal pattern; a first circuit pattern formed on a lower surface of the second insulating layer; and a first via for electrically connecting the first external electrode exposed through the guide hole and the first circuit pattern, and can improve electrical connectivity between the external electrode and the via even when the size of the external electrode of the electronic component is reduced than before.

    Abstract translation: 电子部件嵌入式基板技术领域本发明涉及电子部件嵌入式基板,具备:包括空腔的第一绝缘层; 插入腔内的电子部件; 形成在所述第一绝缘层的下表面上以将所述电子部件安装在其上并且包括用于暴露所述外部电极的一部分的至少一个引导孔的第一金属图案; 形成在所述第一绝缘层的下表面上以覆盖所述第一金属图案的第二绝缘层; 形成在所述第二绝缘层的下表面上的第一电路图案; 以及用于电连接通过引导孔暴露的第一外部电极和第一电路图案的第一通孔,并且即使当电子部件的外部电极的尺寸比以前更小时,也可以改善外部电极和通孔之间的电连接性 。

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