公开(公告)号：USRE37539E1

公开(公告)日：2002-02-05

申请号：US09471000

申请日：1999-12-23

申请人： Satoshi Oguchi ,  Masamichi Ishihara ,  Kazuya Ito ,  Gen Murakami ,  Ichiro Anjoh ,  Toshiyuki Sakuta ,  Yasunori Yamaguchi ,  Yasuhiro Kasama ,  Tetsu Udagawa ,  Eiji Momose ,  Youichi Matsuno ,  Hiroshi Satoh ,  Atsusi Nozoe

发明人： Satoshi Oguchi ,  Masamichi Ishihara ,  Kazuya Ito ,  Gen Murakami ,  Ichiro Anjoh ,  Toshiyuki Sakuta ,  Yasunori Yamaguchi ,  Yasuhiro Kasama ,  Tetsu Udagawa ,  Eiji Momose ,  Youichi Matsuno ,  Hiroshi Satoh ,  Atsusi Nozoe

IPC分类号： H01L2328

CPC分类号： H01L24/06 ,  G11C5/00 ,  G11C5/02 ,  G11C5/06 ,  H01L23/4951 ,  H01L23/49537 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

摘要翻译： 一对DRAM芯片1A和1B通过诸如引线框架之间的布线装置彼此相对地安装，引线框架与外部端子3B基本上成一体。 然后，这些DRAM芯片和引线框架通过常规的引线键合方法连接在一起。 堆叠这样连接的DRAM芯片和引线框架的多对，引线框架的相应引线共同连接以形成层叠体。 这样安装的多个DRAM芯片根据预定的芯片选择信号选择性地被激活。 此外，通过利用上述芯片安装方法，能够正常部分正常工作的部分DRAM芯片组合在一起，以构成单个DRAM封装。

公开(公告)号：US5701031A

公开(公告)日：1997-12-23

申请号：US280381

申请日：1994-07-25

申请人： Satoshi Oguchi ,  Masamichi Ishihara ,  Kazuya Ito ,  Gen Murakami ,  Ichiro Anjoh ,  Toshiyuki Sakuta ,  Yasunori Yamaguchi ,  Yasuhiro Kasama ,  Tetsu Udagawa ,  Eiji Miyamoto ,  Youichi Matsuno ,  Hiroshi Satoh ,  Atsusi Nozoe

发明人： Satoshi Oguchi ,  Masamichi Ishihara ,  Kazuya Ito ,  Gen Murakami ,  Ichiro Anjoh ,  Toshiyuki Sakuta ,  Yasunori Yamaguchi ,  Yasuhiro Kasama ,  Tetsu Udagawa ,  Eiji Miyamoto ,  Youichi Matsuno ,  Hiroshi Satoh ,  Atsusi Nozoe

IPC分类号： G11C5/00 ,  H01L23/495 ,  H01L25/065 ,  H01L23/28 ,  H01L23/535 ,  H01L23/538

CPC分类号： H01L24/06 ,  G11C5/00 ,  G11C5/02 ,  G11C5/06 ,  H01L23/4951 ,  H01L23/49537 ,  H01L23/49575 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181

摘要： A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

摘要翻译： 一对DRAM芯片1A和1B通过诸如引线框架之间的布线装置彼此相对地安装，引线框架与外部端子3B基本上成一体。 然后，这些DRAM芯片和引线框架通过常规的引线键合方法连接在一起。 堆叠这样连接的DRAM芯片和引线框架的多对，并且引线框架的相应引线共同连接以形成层叠体。 这样安装的多个DRAM芯片根据预定的芯片选择信号选择性地被激活。 此外，通过利用上述芯片安装方法，能够正常部分正常工作的部分DRAM芯片组合在一起，以构成单个DRAM封装。

公开(公告)号：US5332922A

公开(公告)日：1994-07-26

申请号：US691985

申请日：1991-04-26

申请人： Satoshi Oguchi ,  Masamichi Ishihara ,  Kazuya Ito ,  Gen Murakami ,  Ichiro Anjoh ,  Toshiyuki Sakuta ,  Yasunori Yamaguchi ,  Yasuhiro Kasama ,  Tetsu Udagawa ,  Eiji Miyamoto ,  Youichi Matsuno ,  Hiroshi Satoh ,  Atsusi Nozoe

发明人： Satoshi Oguchi ,  Masamichi Ishihara ,  Kazuya Ito ,  Gen Murakami ,  Ichiro Anjoh ,  Toshiyuki Sakuta ,  Yasunori Yamaguchi ,  Yasuhiro Kasama ,  Tetsu Udagawa ,  Eiji Miyamoto ,  Youichi Matsuno ,  Hiroshi Satoh ,  Atsusi Nozoe

IPC分类号： G11C5/00 ,  H01L23/495 ,  H01L25/065 ,  H01L23/16 ,  H01L23/48

CPC分类号： H01L24/06 ,  G11C5/00 ,  G11C5/02 ,  G11C5/06 ,  H01L23/4951 ,  H01L23/49537 ,  H01L23/49575 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181

摘要： A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Each chip is bonded with an associated lead frame and each lead frame is disposed as plural lead frame conductors contacting mutually lead frame conductors associated with similarly function bonding pads, i.e. external terminals of the chips, of the other one of the pair of chips. Ones or plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

摘要翻译： 一对DRAM芯片1A和1B通过诸如引线框架之间的布线装置彼此相对地安装，引线框架与外部端子3B基本上成一体。 然后，这些DRAM芯片和引线框架通过常规的引线键合方法连接在一起。 每个芯片与相关联的引线框架结合，并且每个引线框架被设置为与所述一对芯片中的另一个芯片的类似功能键合焊盘（即，芯片的外部端子）相关联的互相引线框架导体的多个引线框架导体。 堆叠这些连接的DRAM芯片和引线框架的一对或多对，并且引线框架的相应引线共同连接以形成层叠体。 这样安装的多个DRAM芯片根据预定的芯片选择信号选择性地被激活。 此外，通过利用上述芯片安装方法，能够正常部分正常工作的部分DRAM芯片组合在一起，以构成单个DRAM封装。

公开(公告)号：US5869888A

公开(公告)日：1999-02-09

申请号：US721339

申请日：1996-09-26

申请人： Kunihiro Tsubosaki ,  Michio Tanimoto ,  Kunihiko Nishi ,  Masahiro Ichitani ,  Shunji Koike ,  Kazunari Suzuki ,  Ryosuke Kimoto ,  Ichiro Anjoh ,  Taisei Jin ,  Akihiko Iwaya ,  Gen Murakami ,  Masamichi Ishihara ,  Junichi Arita

发明人： Kunihiro Tsubosaki ,  Michio Tanimoto ,  Kunihiko Nishi ,  Masahiro Ichitani ,  Shunji Koike ,  Kazunari Suzuki ,  Ryosuke Kimoto ,  Ichiro Anjoh ,  Taisei Jin ,  Akihiko Iwaya ,  Gen Murakami ,  Masamichi Ishihara ,  Junichi Arita

IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L25/10 ,  H01L23/48

CPC分类号： H01L24/06 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4951 ,  H01L24/05 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85424 ,  H01L2225/1029 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/181 ,  H01L2924/351 ,  Y10T29/49121

摘要： A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.

摘要翻译： 一种半导体器件，其具有通过绝缘粘合剂膜固定到半导体芯片的主表面并与半导体芯片的各个外部端子电连接的内部引线。 可以关于芯片尺寸的半导体器件被配置为使得外引线从每个内引线连续地延伸到与半导体芯片的主表面相对的后表面，以便保持引线和外部器件 导通。

公开(公告)号：US5714405A

公开(公告)日：1998-02-03

申请号：US721240

申请日：1996-09-26

申请人： Kunihiro Tsubosaki ,  Michio Tanimoto ,  Kunihiko Nishi ,  Masahiro Ichitani ,  Shunji Koike ,  Kazunari Suzuki ,  Ryosuke Kimoto ,  Ichiro Anjoh ,  Taisei Jin ,  Akihiko Iwaya ,  Gen Murakami ,  Masamichi Ishihara ,  Junichi Arita

发明人： Kunihiro Tsubosaki ,  Michio Tanimoto ,  Kunihiko Nishi ,  Masahiro Ichitani ,  Shunji Koike ,  Kazunari Suzuki ,  Ryosuke Kimoto ,  Ichiro Anjoh ,  Taisei Jin ,  Akihiko Iwaya ,  Gen Murakami ,  Masamichi Ishihara ,  Junichi Arita

IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L25/10 ,  H01L21/60

CPC分类号： H01L24/06 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4951 ,  H01L24/05 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85424 ,  H01L2225/1029 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/181 ,  H01L2924/351 ,  Y10T29/49121

摘要： A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.

摘要翻译： 一种半导体器件，其具有通过绝缘粘合剂膜固定到半导体芯片的主表面并与半导体芯片的各个外部端子电连接的内部引线。 可以关于芯片尺寸的半导体器件被配置为使得外引线从每个内引线连续地延伸到与半导体芯片的主表面相对的后表面，以便保持引线和外部器件 导通。

公开(公告)号：US5583375A

公开(公告)日：1996-12-10

申请号：US990633

申请日：1992-12-14

申请人： Kunihiro Tsubosaki ,  Michio Tanimoto ,  Kunihiko Nishi ,  Masahiro Ichitani ,  Shunji Koike ,  Kazunari Suzuki ,  Ryosuke Kimoto ,  Ichiro Anjoh ,  Taisei Jin ,  Akihiko Iwaya ,  Gen Murakami ,  Masamichi Ishihara ,  Junichi Arita

发明人： Kunihiro Tsubosaki ,  Michio Tanimoto ,  Kunihiko Nishi ,  Masahiro Ichitani ,  Shunji Koike ,  Kazunari Suzuki ,  Ryosuke Kimoto ,  Ichiro Anjoh ,  Taisei Jin ,  Akihiko Iwaya ,  Gen Murakami ,  Masamichi Ishihara ,  Junichi Arita

IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L25/10 ,  H01L23/48

CPC分类号： H01L24/06 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4951 ,  H01L24/05 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85424 ,  H01L2225/1029 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/181 ,  H01L2924/351 ,  Y10T29/49121

摘要： A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.

摘要翻译： 一种半导体器件，其具有通过绝缘粘合剂膜固定到半导体芯片的主表面并与半导体芯片的各个外部端子电连接的内部引线。 可以关于芯片尺寸的半导体器件被配置为使得外引线从每个内引线连续地延伸到与半导体芯片的主表面相对的后表面，以便保持引线和外部器件 导通。

公开(公告)号：US4951122A

公开(公告)日：1990-08-21

申请号：US199538

申请日：1988-05-27

申请人： Kunihiro Tsubosaki ,  Gen Murakami ,  Toshiyuki Sakuta ,  Masamichi Ishihara ,  Satoru Ito ,  Yasuo Mori

发明人： Kunihiro Tsubosaki ,  Gen Murakami ,  Toshiyuki Sakuta ,  Masamichi Ishihara ,  Satoru Ito ,  Yasuo Mori

IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L23/498

CPC分类号： H01L24/32 ,  H01L23/3135 ,  H01L23/49506 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49558 ,  H01L23/49861 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3011 ,  H01L2924/351

摘要： The present invention relates to a technique in which the pellet fixing parts of a lead frame of the tabless type or the type having no die pads are molded in or coated with a resin beforehand in order to enhance the reliability of a resin-encapsulated IC having become important with enlargement in the size of the chip of a memory IC or the like and reduction in the size of a resin package, and a resin package structure in which the technique of the lead frame having no die pads is applied to flat packaging so as to lessen reflow cracks.

摘要翻译： 本发明涉及一种技术，其中预先将无凸型引线框架或不具有模片焊盘的引线框架的芯片固定部件预先模制或涂覆树脂，以提高具有树脂封装的IC的可靠性 随着存储器IC等的芯片的尺寸的增大和树脂封装的尺寸的减小而变得重要，并且将没有管芯焊盘的引线框架的技术应用于平面封装的树脂封装结构，因此 以减少回流裂纹。

公开(公告)号：US5514905A

公开(公告)日：1996-05-07

申请号：US329824

申请日：1994-10-27

申请人： Toshiyuki Sakuta ,  Kazuyuki Miyazawa ,  Satoshi Oguchi ,  Aizo Kaneda ,  Masao Mitani ,  Shozo Nakamura ,  Kunihiko Nishi ,  Gen Murakami

发明人： Toshiyuki Sakuta ,  Kazuyuki Miyazawa ,  Satoshi Oguchi ,  Aizo Kaneda ,  Masao Mitani ,  Shozo Nakamura ,  Kunihiko Nishi ,  Gen Murakami

IPC分类号： H01L23/29 ,  H01L23/495 ,  H01L23/48 ,  H01L29/41

CPC分类号： H01L23/4951 ,  H01L23/293 ,  H01L2224/05599 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48599 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14

摘要： A semiconductor device is provided in connection with a semiconductor chip which has a plurality of bonding pads at a part corresponding to a centrally located area of the front or first main surface thereof, an organic insulator film which overlies the semiconductor chip and which has an opening in correspondence with the bonding pads, a plurality of leads which overly the organic insulator film, and a molding resin with which these constituents are sealed or packaged.

摘要翻译： 半导体器件与半导体芯片相连，该半导体芯片在与其前表面或第一主表面的中心位置相对应的部分处具有多个接合焊盘;半导体芯片，覆盖在半导体芯片上并具有开口 与接合焊盘相对应，多个有机绝缘膜上的引线以及密封或封装这些成分的成型树脂。

公开(公告)号：US5184208A

公开(公告)日：1993-02-02

申请号：US640584

申请日：1991-01-14

申请人： Toshiyuki Sakuta ,  Kazuyuki Miyazawa ,  Satoshi Oguchi ,  Aizo Kaneda ,  Masao Mitani ,  Shozo Nakamura ,  Kunihiko Nishi ,  Gen Murakami

发明人： Toshiyuki Sakuta ,  Kazuyuki Miyazawa ,  Satoshi Oguchi ,  Aizo Kaneda ,  Masao Mitani ,  Shozo Nakamura ,  Kunihiko Nishi ,  Gen Murakami

IPC分类号： H01L23/29 ,  H01L23/495

CPC分类号： H01L23/293 ,  H01L23/4951 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48599 ,  H01L2224/73215 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181

摘要： A semiconductor device is provided in connection with a semiconductor chip which has a plurality of bonding pads at a part corresponding to a centrally located area of the front or first main surface thereof, an organic insulator film which overlies the semiconductor chip and which has an opening in correspondence with the bonding pads, a plurality of leads which overly the organic insulator film, and a molding resin with which these constituents are sealed or packaged.

摘要翻译： 半导体器件与半导体芯片相连，该半导体芯片在与其前表面或第一主表面的中心位置相对应的部分处具有多个接合焊盘;半导体芯片，覆盖在半导体芯片上并具有开口 与接合焊盘相对应，多个有机绝缘膜上的引线，以及密封或封装这些成分的成型树脂。

公开(公告)号：US5742101A

公开(公告)日：1998-04-21

申请号：US458166

申请日：1995-06-02

申请人： Toshiyuki Sakuta ,  Kazuyuki Miyazawa ,  Satoshi Oguchi ,  Aizo Kaneda ,  Masao Mitani ,  Shozo Nakamura ,  Kunihiko Nishi ,  Gen Murakami

发明人： Toshiyuki Sakuta ,  Kazuyuki Miyazawa ,  Satoshi Oguchi ,  Aizo Kaneda ,  Masao Mitani ,  Shozo Nakamura ,  Kunihiko Nishi ,  Gen Murakami

IPC分类号： H01L23/29 ,  H01L23/495 ,  H01L23/48 ,  H01L23/02 ,  H01L29/46

CPC分类号： H01L23/4951 ,  H01L23/293 ,  H01L2224/05599 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48599 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14

摘要： A semiconductor device is provided in connection with a semiconductor chip which has a plurality of bonding pads at a part corresponding to a centrally located area of the front or first main surface thereof, an organic insulator film which overlies the semiconductor chip and which has an opening in correspondence with the bonding pads, a plurality of leads which overly the organic insulator film, and a molding resin with which these constituents are sealed or packaged.