公开(公告)号：US4951122A

公开(公告)日：1990-08-21

申请号：US199538

申请日：1988-05-27

申请人： Kunihiro Tsubosaki ,  Gen Murakami ,  Toshiyuki Sakuta ,  Masamichi Ishihara ,  Satoru Ito ,  Yasuo Mori

发明人： Kunihiro Tsubosaki ,  Gen Murakami ,  Toshiyuki Sakuta ,  Masamichi Ishihara ,  Satoru Ito ,  Yasuo Mori

IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L23/498

CPC分类号： H01L24/32 ,  H01L23/3135 ,  H01L23/49506 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49558 ,  H01L23/49861 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3011 ,  H01L2924/351

摘要： The present invention relates to a technique in which the pellet fixing parts of a lead frame of the tabless type or the type having no die pads are molded in or coated with a resin beforehand in order to enhance the reliability of a resin-encapsulated IC having become important with enlargement in the size of the chip of a memory IC or the like and reduction in the size of a resin package, and a resin package structure in which the technique of the lead frame having no die pads is applied to flat packaging so as to lessen reflow cracks.

摘要翻译： 本发明涉及一种技术，其中预先将无凸型引线框架或不具有模片焊盘的引线框架的芯片固定部件预先模制或涂覆树脂，以提高具有树脂封装的IC的可靠性 随着存储器IC等的芯片的尺寸的增大和树脂封装的尺寸的减小而变得重要，并且将没有管芯焊盘的引线框架的技术应用于平面封装的树脂封装结构，因此 以减少回流裂纹。

公开(公告)号：US5714405A

公开(公告)日：1998-02-03

申请号：US721240

申请日：1996-09-26

申请人： Kunihiro Tsubosaki ,  Michio Tanimoto ,  Kunihiko Nishi ,  Masahiro Ichitani ,  Shunji Koike ,  Kazunari Suzuki ,  Ryosuke Kimoto ,  Ichiro Anjoh ,  Taisei Jin ,  Akihiko Iwaya ,  Gen Murakami ,  Masamichi Ishihara ,  Junichi Arita

发明人： Kunihiro Tsubosaki ,  Michio Tanimoto ,  Kunihiko Nishi ,  Masahiro Ichitani ,  Shunji Koike ,  Kazunari Suzuki ,  Ryosuke Kimoto ,  Ichiro Anjoh ,  Taisei Jin ,  Akihiko Iwaya ,  Gen Murakami ,  Masamichi Ishihara ,  Junichi Arita

IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L25/10 ,  H01L21/60

CPC分类号： H01L24/06 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4951 ,  H01L24/05 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85424 ,  H01L2225/1029 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/181 ,  H01L2924/351 ,  Y10T29/49121

摘要： A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.

摘要翻译： 一种半导体器件，其具有通过绝缘粘合剂膜固定到半导体芯片的主表面并与半导体芯片的各个外部端子电连接的内部引线。 可以关于芯片尺寸的半导体器件被配置为使得外引线从每个内引线连续地延伸到与半导体芯片的主表面相对的后表面，以便保持引线和外部器件 导通。

公开(公告)号：US5869888A

公开(公告)日：1999-02-09

申请号：US721339

申请日：1996-09-26

申请人： Kunihiro Tsubosaki ,  Michio Tanimoto ,  Kunihiko Nishi ,  Masahiro Ichitani ,  Shunji Koike ,  Kazunari Suzuki ,  Ryosuke Kimoto ,  Ichiro Anjoh ,  Taisei Jin ,  Akihiko Iwaya ,  Gen Murakami ,  Masamichi Ishihara ,  Junichi Arita

发明人： Kunihiro Tsubosaki ,  Michio Tanimoto ,  Kunihiko Nishi ,  Masahiro Ichitani ,  Shunji Koike ,  Kazunari Suzuki ,  Ryosuke Kimoto ,  Ichiro Anjoh ,  Taisei Jin ,  Akihiko Iwaya ,  Gen Murakami ,  Masamichi Ishihara ,  Junichi Arita

IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L25/10 ,  H01L23/48

CPC分类号： H01L24/06 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4951 ,  H01L24/05 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85424 ,  H01L2225/1029 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/181 ,  H01L2924/351 ,  Y10T29/49121

摘要： A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.

摘要翻译： 一种半导体器件，其具有通过绝缘粘合剂膜固定到半导体芯片的主表面并与半导体芯片的各个外部端子电连接的内部引线。 可以关于芯片尺寸的半导体器件被配置为使得外引线从每个内引线连续地延伸到与半导体芯片的主表面相对的后表面，以便保持引线和外部器件 导通。

公开(公告)号：US5583375A

公开(公告)日：1996-12-10

申请号：US990633

申请日：1992-12-14

申请人： Kunihiro Tsubosaki ,  Michio Tanimoto ,  Kunihiko Nishi ,  Masahiro Ichitani ,  Shunji Koike ,  Kazunari Suzuki ,  Ryosuke Kimoto ,  Ichiro Anjoh ,  Taisei Jin ,  Akihiko Iwaya ,  Gen Murakami ,  Masamichi Ishihara ,  Junichi Arita

发明人： Kunihiro Tsubosaki ,  Michio Tanimoto ,  Kunihiko Nishi ,  Masahiro Ichitani ,  Shunji Koike ,  Kazunari Suzuki ,  Ryosuke Kimoto ,  Ichiro Anjoh ,  Taisei Jin ,  Akihiko Iwaya ,  Gen Murakami ,  Masamichi Ishihara ,  Junichi Arita

IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L25/10 ,  H01L23/48

CPC分类号： H01L24/06 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4951 ,  H01L24/05 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85424 ,  H01L2225/1029 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/181 ,  H01L2924/351 ,  Y10T29/49121

摘要： A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.

摘要翻译： 一种半导体器件，其具有通过绝缘粘合剂膜固定到半导体芯片的主表面并与半导体芯片的各个外部端子电连接的内部引线。 可以关于芯片尺寸的半导体器件被配置为使得外引线从每个内引线连续地延伸到与半导体芯片的主表面相对的后表面，以便保持引线和外部器件 导通。

公开(公告)号：US5332922A

公开(公告)日：1994-07-26

申请号：US691985

申请日：1991-04-26

申请人： Satoshi Oguchi ,  Masamichi Ishihara ,  Kazuya Ito ,  Gen Murakami ,  Ichiro Anjoh ,  Toshiyuki Sakuta ,  Yasunori Yamaguchi ,  Yasuhiro Kasama ,  Tetsu Udagawa ,  Eiji Miyamoto ,  Youichi Matsuno ,  Hiroshi Satoh ,  Atsusi Nozoe

发明人： Satoshi Oguchi ,  Masamichi Ishihara ,  Kazuya Ito ,  Gen Murakami ,  Ichiro Anjoh ,  Toshiyuki Sakuta ,  Yasunori Yamaguchi ,  Yasuhiro Kasama ,  Tetsu Udagawa ,  Eiji Miyamoto ,  Youichi Matsuno ,  Hiroshi Satoh ,  Atsusi Nozoe

IPC分类号： G11C5/00 ,  H01L23/495 ,  H01L25/065 ,  H01L23/16 ,  H01L23/48

CPC分类号： H01L24/06 ,  G11C5/00 ,  G11C5/02 ,  G11C5/06 ,  H01L23/4951 ,  H01L23/49537 ,  H01L23/49575 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181

摘要： A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Each chip is bonded with an associated lead frame and each lead frame is disposed as plural lead frame conductors contacting mutually lead frame conductors associated with similarly function bonding pads, i.e. external terminals of the chips, of the other one of the pair of chips. Ones or plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

摘要翻译： 一对DRAM芯片1A和1B通过诸如引线框架之间的布线装置彼此相对地安装，引线框架与外部端子3B基本上成一体。 然后，这些DRAM芯片和引线框架通过常规的引线键合方法连接在一起。 每个芯片与相关联的引线框架结合，并且每个引线框架被设置为与所述一对芯片中的另一个芯片的类似功能键合焊盘（即，芯片的外部端子）相关联的互相引线框架导体的多个引线框架导体。 堆叠这些连接的DRAM芯片和引线框架的一对或多对，并且引线框架的相应引线共同连接以形成层叠体。 这样安装的多个DRAM芯片根据预定的芯片选择信号选择性地被激活。 此外，通过利用上述芯片安装方法，能够正常部分正常工作的部分DRAM芯片组合在一起，以构成单个DRAM封装。

公开(公告)号：US5701031A

公开(公告)日：1997-12-23

申请号：US280381

申请日：1994-07-25

申请人： Satoshi Oguchi ,  Masamichi Ishihara ,  Kazuya Ito ,  Gen Murakami ,  Ichiro Anjoh ,  Toshiyuki Sakuta ,  Yasunori Yamaguchi ,  Yasuhiro Kasama ,  Tetsu Udagawa ,  Eiji Miyamoto ,  Youichi Matsuno ,  Hiroshi Satoh ,  Atsusi Nozoe

发明人： Satoshi Oguchi ,  Masamichi Ishihara ,  Kazuya Ito ,  Gen Murakami ,  Ichiro Anjoh ,  Toshiyuki Sakuta ,  Yasunori Yamaguchi ,  Yasuhiro Kasama ,  Tetsu Udagawa ,  Eiji Miyamoto ,  Youichi Matsuno ,  Hiroshi Satoh ,  Atsusi Nozoe

IPC分类号： G11C5/00 ,  H01L23/495 ,  H01L25/065 ,  H01L23/28 ,  H01L23/535 ,  H01L23/538

CPC分类号： H01L24/06 ,  G11C5/00 ,  G11C5/02 ,  G11C5/06 ,  H01L23/4951 ,  H01L23/49537 ,  H01L23/49575 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181

摘要： A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

摘要翻译： 一对DRAM芯片1A和1B通过诸如引线框架之间的布线装置彼此相对地安装，引线框架与外部端子3B基本上成一体。 然后，这些DRAM芯片和引线框架通过常规的引线键合方法连接在一起。 堆叠这样连接的DRAM芯片和引线框架的多对，并且引线框架的相应引线共同连接以形成层叠体。 这样安装的多个DRAM芯片根据预定的芯片选择信号选择性地被激活。 此外，通过利用上述芯片安装方法，能够正常部分正常工作的部分DRAM芯片组合在一起，以构成单个DRAM封装。

公开(公告)号：USRE37539E1

公开(公告)日：2002-02-05

申请号：US09471000

申请日：1999-12-23

申请人： Satoshi Oguchi ,  Masamichi Ishihara ,  Kazuya Ito ,  Gen Murakami ,  Ichiro Anjoh ,  Toshiyuki Sakuta ,  Yasunori Yamaguchi ,  Yasuhiro Kasama ,  Tetsu Udagawa ,  Eiji Momose ,  Youichi Matsuno ,  Hiroshi Satoh ,  Atsusi Nozoe

发明人： Satoshi Oguchi ,  Masamichi Ishihara ,  Kazuya Ito ,  Gen Murakami ,  Ichiro Anjoh ,  Toshiyuki Sakuta ,  Yasunori Yamaguchi ,  Yasuhiro Kasama ,  Tetsu Udagawa ,  Eiji Momose ,  Youichi Matsuno ,  Hiroshi Satoh ,  Atsusi Nozoe

IPC分类号： H01L2328

CPC分类号： H01L24/06 ,  G11C5/00 ,  G11C5/02 ,  G11C5/06 ,  H01L23/4951 ,  H01L23/49537 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

摘要翻译： 一对DRAM芯片1A和1B通过诸如引线框架之间的布线装置彼此相对地安装，引线框架与外部端子3B基本上成一体。 然后，这些DRAM芯片和引线框架通过常规的引线键合方法连接在一起。 堆叠这样连接的DRAM芯片和引线框架的多对，引线框架的相应引线共同连接以形成层叠体。 这样安装的多个DRAM芯片根据预定的芯片选择信号选择性地被激活。 此外，通过利用上述芯片安装方法，能够正常部分正常工作的部分DRAM芯片组合在一起，以构成单个DRAM封装。

公开(公告)号：US5359561A

公开(公告)日：1994-10-25

申请号：US872958

申请日：1992-04-23

申请人： Shigetoshi Sakomura ,  Kazuya Ito ,  Hidetoshi Iwai ,  Toshiyuki Sakuta ,  Masamichi Ishihara ,  Tomoshi Matsumoto, deceased

发明人： Shigetoshi Sakomura ,  Kazuya Ito ,  Hidetoshi Iwai ,  Toshiyuki Sakuta ,  Masamichi Ishihara ,  Tomoshi Matsumoto, deceased

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  G11C7/00

CPC分类号： G11C29/24

摘要： A semiconductor memory device is provided which includes a plurality of data lines, at least one redundant data line, one common data line, a plurality of column switches installed between the plurality of data lines and the redundant data line and one common data line, and a column decoder for controlling the plurality of column switches. The column decoder operates to turn the column switch on. The column switch is connected to a plurality of data lines, excluding any defective data and redundant data lines during the test mode state.

摘要翻译： 提供一种半导体存储器件，其包括多个数据线，至少一个冗余数据线，一个公共数据线，安装在多个数据线与冗余数据线和一条公共数据线之间的多个列开关，以及 用于控制多个列开关的列解码器。 列解码器操作以打开列开关。 列开关连接到多个数据线，在测试模式状态期间不包括任何有缺陷的数据和冗余数据线。

公开(公告)号：US4991139A

公开(公告)日：1991-02-05

申请号：US228022

申请日：1988-08-04

申请人： Yasushi Takahashi ,  Masamichi Ishihara ,  Kazuhiko Kajigaya ,  Toshiyuki Sakuta

发明人： Yasushi Takahashi ,  Masamichi Ishihara ,  Kazuhiko Kajigaya ,  Toshiyuki Sakuta

IPC分类号： G11C29/04 ,  G11C29/34 ,  G11C29/38

CPC分类号： G11C29/34 ,  G11C29/04 ,  G11C29/38

摘要： A semiconductor memory device is provided which includes a plurality of data lines coupled to memory cells and to a detecting arrangement for detecting if logical levels of each of the data lines coincide to each other or not. A test read arrangement is also provided which stores the same information, in advance, in plural memory cells so that if there is a defect in one of the memory cells, this can be detected by the detecting arrangement.

摘要翻译： 提供一种半导体存储器件，其包括耦合到存储器单元的多条数据线以及用于检测每条数据线的逻辑电平是否彼此一致的检测装置。 还提供了一种测试读取装置，其预先在多个存储单元中存储相同的信息，使得如果存储单元之一存在缺陷，则可以通过检测装置来检测。

公开(公告)号：US5208782A

公开(公告)日：1993-05-04

申请号：US892708

申请日：1992-05-29

申请人： Toshiyuki Sakuta ,  Masamichi Ishihara ,  Kazuyuki Miyazawa ,  Masanori Tazunoki ,  Hidetoshi Iwai ,  Hisashi Nakamura ,  Yasushi Takahashi ,  Toshio Maeda ,  Hiromi Matsuura ,  Ryoichi Hori ,  Toshio Sasaki ,  Osamu Sakai ,  Hiroyuki Uchiyama ,  Eiji Miyamoto ,  Kazuyoshi Oshima ,  Yasuhiro Kasama

发明人： Toshiyuki Sakuta ,  Masamichi Ishihara ,  Kazuyuki Miyazawa ,  Masanori Tazunoki ,  Hidetoshi Iwai ,  Hisashi Nakamura ,  Yasushi Takahashi ,  Toshio Maeda ,  Hiromi Matsuura ,  Ryoichi Hori ,  Toshio Sasaki ,  Osamu Sakai ,  Hiroyuki Uchiyama ,  Eiji Miyamoto ,  Kazuyoshi Oshima ,  Yasuhiro Kasama

IPC分类号： G06F11/18 ,  G06F11/20 ,  G11C11/406 ,  G11C29/00 ,  H01L27/105 ,  H01L27/108

CPC分类号： G11C29/808 ,  G11C11/406 ,  G11C29/88 ,  H01L24/06 ,  H01L27/10805 ,  G06F11/1666 ,  G06F11/183 ,  H01L2224/4826 ,  H01L27/105 ,  H01L2924/13091 ,  H01L2924/14

摘要： A semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip. To achieve, this, a plurality of macro-cellulated memory blocks can be provided, with each of the memory blocks including a memory array as well as additional circuitry such as address selection circuits and input/output circuits. Other peripheral circuits are provided on the chip which are common to the plurality of macro-cell memory blocks. The macro-cell memory blocks themselves can be formed in an array so that their combined storage capacity will form the large overall storage capacity of the chip. The combination of the macro-cell memory blocks and the common peripheral circuitry for controlling the memory blocks permits a faster and more efficient refreshing operation for a DRAM. This is enhanced by a LOC (Lead On Chip) arrangement used in conjunction with the memory blocks.

摘要翻译： 提供了一种半导体集成电路存储器结构，其使用宏单元电路块，其可以在单个芯片上允许非常大的存储能力（例如，DRAM中的64Mbits）。 为了实现这一点，可以提供多个宏单元存储器块，其中每个存储器块包括存储器阵列以及诸如地址选择电路和输入/输出电路的附加电路。 在芯片上提供了多个宏单元存储块通用的其他外围电路。 宏单元存储器块本身可以形成为阵列，使得它们的组合存储容量将形成芯片的大的总体存储容量。 宏单元存储器块和用于控制存储器块的公共外围电路的组合允许DRAM的更快更有效的刷新操作。 这通过与存储器块结合使用的LOC（片上芯片）布置来增强。