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公开(公告)号：USRE37539E1
公开(公告)日：2002-02-05
申请号：US09471000
申请日：1999-12-23
申请人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Momose , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
发明人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Momose , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
IPC分类号： H01L2328
CPC分类号： H01L24/06 , G11C5/00 , G11C5/02 , G11C5/06 , H01L23/4951 , H01L23/49537 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2225/1029 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01047 , H01L2924/01055 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.
摘要翻译： 一对DRAM芯片1A和1B通过诸如引线框架之间的布线装置彼此相对地安装，引线框架与外部端子3B基本上成一体。 然后，这些DRAM芯片和引线框架通过常规的引线键合方法连接在一起。 堆叠这样连接的DRAM芯片和引线框架的多对，引线框架的相应引线共同连接以形成层叠体。 这样安装的多个DRAM芯片根据预定的芯片选择信号选择性地被激活。 此外，通过利用上述芯片安装方法，能够正常部分正常工作的部分DRAM芯片组合在一起，以构成单个DRAM封装。
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公开(公告)号：US5701031A
公开(公告)日：1997-12-23
申请号：US280381
申请日：1994-07-25
申请人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Miyamoto , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
发明人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Miyamoto , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
IPC分类号： G11C5/00 , H01L23/495 , H01L25/065 , H01L23/28 , H01L23/535 , H01L23/538
CPC分类号： H01L24/06 , G11C5/00 , G11C5/02 , G11C5/06 , H01L23/4951 , H01L23/49537 , H01L23/49575 , H01L25/0652 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01047 , H01L2924/01055 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181
摘要： A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.
摘要翻译： 一对DRAM芯片1A和1B通过诸如引线框架之间的布线装置彼此相对地安装，引线框架与外部端子3B基本上成一体。 然后，这些DRAM芯片和引线框架通过常规的引线键合方法连接在一起。 堆叠这样连接的DRAM芯片和引线框架的多对，并且引线框架的相应引线共同连接以形成层叠体。 这样安装的多个DRAM芯片根据预定的芯片选择信号选择性地被激活。 此外，通过利用上述芯片安装方法，能够正常部分正常工作的部分DRAM芯片组合在一起，以构成单个DRAM封装。
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公开(公告)号：US5332922A
公开(公告)日：1994-07-26
申请号：US691985
申请日：1991-04-26
申请人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Miyamoto , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
发明人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Miyamoto , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
IPC分类号： G11C5/00 , H01L23/495 , H01L25/065 , H01L23/16 , H01L23/48
CPC分类号： H01L24/06 , G11C5/00 , G11C5/02 , G11C5/06 , H01L23/4951 , H01L23/49537 , H01L23/49575 , H01L25/0652 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01047 , H01L2924/01055 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181
摘要： A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Each chip is bonded with an associated lead frame and each lead frame is disposed as plural lead frame conductors contacting mutually lead frame conductors associated with similarly function bonding pads, i.e. external terminals of the chips, of the other one of the pair of chips. Ones or plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.
摘要翻译： 一对DRAM芯片1A和1B通过诸如引线框架之间的布线装置彼此相对地安装，引线框架与外部端子3B基本上成一体。 然后，这些DRAM芯片和引线框架通过常规的引线键合方法连接在一起。 每个芯片与相关联的引线框架结合，并且每个引线框架被设置为与所述一对芯片中的另一个芯片的类似功能键合焊盘（即，芯片的外部端子）相关联的互相引线框架导体的多个引线框架导体。 堆叠这些连接的DRAM芯片和引线框架的一对或多对，并且引线框架的相应引线共同连接以形成层叠体。 这样安装的多个DRAM芯片根据预定的芯片选择信号选择性地被激活。 此外，通过利用上述芯片安装方法，能够正常部分正常工作的部分DRAM芯片组合在一起，以构成单个DRAM封装。
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公开(公告)号：US6108264A
公开(公告)日：2000-08-22
申请号：US234101
申请日：1999-01-19
IPC分类号： G11C7/00 , G11C7/06 , G11C11/406
CPC分类号： G11C7/06 , G11C11/406
摘要： An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or, in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.
摘要翻译： 普通的读/写操作（正常操作）和刷新操作彼此分离，并且读取的放大电路的数量，或者换句话说，使得在正常操作期间操作的读出放大器的数量小于刷新期间的读出放大器的数量 操作。 因此，可以减少正常工作期间的位线充电/放电电流。
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公开(公告)号：US5043947A
公开(公告)日：1991-08-27
申请号：US530304
申请日：1990-05-30
IPC分类号： G11C11/401 , G11C8/12 , G11C11/407 , G11C11/409
CPC分类号： G11C8/12 , G11C11/407
摘要： A memory device is provided including a plurality of memory arrays and peripheral circuits. For example, in a dynamic RAM the peripheral circuitry will include row address decoders, column address decoders, sense amplifiers and main amplifiers disposed in such a manner as to correspond to the memory arrays, respectively. The desired row address decoders, column address decoders, sense amplifiers and main amplifiers are selectively operated in accordance with a common array selection signal generated on the basis of at least part of row address signals. Accordingly, only the row address decoders, column address decoders, sense amplifiers and main amplifiers corresponding to the memory array containing the designated memory cells are operated selectively in accordance with the common array selection signal. It is thus possible to reduce power consumption of the dynamic RAM and to simplify the structure of the peripheral circuits and wirings.
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公开(公告)号：US4941129A
公开(公告)日：1990-07-10
申请号：US237051
申请日：1988-08-29
IPC分类号： G11C11/401 , G11C8/12 , G11C11/407 , G11C11/409
CPC分类号： G11C8/12 , G11C11/407
摘要： A memory device is provided including a plurality of memory arrays and peripheral circuits. For example, in a dynamic RAM the peripheral circuitry will include row address decoders, column address decoders, sense amplifiers and main amplifiers disposed in such a manner as to correspond to the memory arrays, respectively. The desired row address decoders, column address decoders, sense amplifiers and main amplifiers are selectively operated in accordance with a common array selection signal generated on the basis of at least part of row address signals. Accordingly, only the row address decoders, column address decoders, sense amplifiers and main amplifiers corresponding to the memory array containing the designated memory cells are operated selectively in accordance with the common array selection signal. It is thus possible to reduce power consumption of the dynamic RAM and to simplify the structure of the peripheral circuits and wirings.
摘要翻译： 提供了包括多个存储器阵列和外围电路的存储器件。 例如，在动态RAM中，外围电路将包括分别以对应于存储器阵列的方式设置的行地址解码器，列地址解码器，读出放大器和主放大器。 根据至少部分行地址信号产生的公共阵列选择信号选择性地操作所需的行地址解码器，列地址解码器，读出放大器和主放大器。 因此，仅根据公共阵列选择信号有选择地操作与包含指定的存储单元的存储器阵列对应的行地址解码器，列地址解码器，读出放大器和主放大器。 因此，可以降低动态RAM的功耗，并且简化外围电路和配线的结构。
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7.发明授权Semiconductor memory having both a refresh operation cycle and a normal operation cycle and employing an address non-multiplex system 失效半导体存储器具有刷新操作周期和正常操作周期，并采用地址非复用系统
公开(公告)号：US5862095A
公开(公告)日：1999-01-19
申请号：US962351
申请日：1997-10-31
IPC分类号： G11C7/00 , G11C7/06 , G11C11/406
CPC分类号： G11C7/06 , G11C11/406
摘要： An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.
摘要翻译： 普通的读/写操作（正常操作）和刷新操作彼此分离，读取的放大电路的数量或换句话说，在正常操作期间操作的读出放大器的数量小于刷新操作期间的读出放大器的数量 。 因此，可以减少正常工作期间的位线充电/放电电流。
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8.发明授权Semiconductor memory having a refresh operation cycle and operating at a high speed and reduced power consumption in a normal operation cycle 失效半导体存储器具有刷新操作周期并且在正常操作周期中高速运行并降低功耗
公开(公告)号：US5719815A
公开(公告)日：1998-02-17
申请号：US503738
申请日：1995-07-18
IPC分类号： G11C7/00 , G11C7/06 , G11C11/406
CPC分类号： G11C7/06 , G11C11/406
摘要： An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or, in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.
摘要翻译： 普通的读/写操作（正常操作）和刷新操作彼此分离，并且读取的放大电路的数量，或者换句话说，使得在正常操作期间操作的读出放大器的数量小于刷新期间的读出放大器的数量 操作。 因此，可以减少正常工作期间的位线充电/放电电流。
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公开(公告)号：US5506804A
公开(公告)日：1996-04-09
申请号：US159205
申请日：1993-11-30
申请人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
发明人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
IPC分类号： G11C11/409 , G05F3/24 , G11C11/401 , G11C11/403 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C29/80 , G11C11/4085 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , G11C11/401
摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.
摘要翻译： 提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。 为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。 此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。 读取信号作为电流信号传输，然后转换为电压信号，以提高读取速度。 此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。
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10.发明授权公开(公告)号：US06635918B1
公开(公告)日：2003-10-21
申请号：US09714127
申请日：2000-11-17
申请人： Seiji Narui , Tetsu Udagawa , Kazuhiko Kajigaya , Makoto Yoshida
发明人： Seiji Narui , Tetsu Udagawa , Kazuhiko Kajigaya , Makoto Yoshida
IPC分类号： H01L27108
CPC分类号： H01L27/10894 , H01L27/10814 , H01L27/10873 , H01L27/10882 , H01L27/10885 , H01L2924/0002 , Y10S257/915 , H01L2924/00
摘要： The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL1, BL2 are, respectively, 2 &OHgr;/□ or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL1, BL2 by which the number of the steps of manufacturing the DRAM can be reduced.
摘要翻译： 存储单元选择MISFET Q，DRAM的栅电极8A（字线）和位线BL1，BL2的薄层电阻的薄层电阻分别为2Ω/□以下。 在形成栅电极8A（字线WL）或位线BL1，BL2的步骤期间形成外围电路的互连，通过该位线可以减少制造DRAM的步骤的数量。
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