公开(公告)号：US20130147062A1

公开(公告)日：2013-06-13

申请号：US13567046

申请日：2012-08-04

Applicant: Hee-Jin LEE ,  Woo-Dong LEE

Inventor： Hee-Jin LEE ,  Woo-Dong LEE

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L21/50 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A multi-chip package may include a package substrate, a first semiconductor chip, a second semiconductor chip and a supporting member. The first semiconductor chip may be arranged on an upper surface of the package substrate. The first semiconductor chip may be electrically connected with the package substrate. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The second semiconductor chip may be electrically connected with the first semiconductor chip. The second semiconductor chip may have a protrusion overhanging an area beyond a side surface of the first semiconductor chip. The supporting member may be interposed between the protrusion of the second semiconductor chip and the package substrate to prevent a deflection of the protrusion. Thus, the protrusion may not be deflected.

Abstract translation: 多芯片封装可以包括封装衬底，第一半导体芯片，第二半导体芯片和支撑构件。 第一半导体芯片可以布置在封装衬底的上表面上。 第一半导体芯片可以与封装衬底电连接。 第二半导体芯片可以布置在第一半导体芯片的上表面上。 第二半导体芯片可以与第一半导体芯片电连接。 第二半导体芯片可以具有突出超过第一半导体芯片的侧表面的区域的突起。 支撑构件可以插入在第二半导体芯片的突起与封装基板之间，以防止突起的偏转。 因此，突起可能不会偏转。

公开(公告)号：US20120205250A1

公开(公告)日：2012-08-16

申请号：US13083262

申请日：2011-04-08

Applicant: Hee Jin Lee ,  Dong Hyun Cho ,  Ji Eun Jeon

Inventor： Hee Jin Lee ,  Dong Hyun Cho ,  Ji Eun Jeon

IPC: C25D3/38

CPC classification number: C25D3/38

Abstract: Disclosed is an electrolytic copper plating solution composition, which includes a copper salt, an acidic solution, and a PEG-PPG-PEG copolymer, and in which the PEG-PPG-PEG copolymer which is a non-ionic surfactant is added, thus decreasing the surface tension of the electrolytic copper plating solution, thereby enhancing plating wettability.

Abstract translation: 公开了一种电解铜电镀液组合物，其包含铜盐，酸性溶液和PEG-PPG-PEG共聚物，其中加入作为非离子表面活性剂的PEG-PPG-PEG共聚物，因此减少 电解铜电镀液的表面张力，从而提高电镀润湿性。

公开(公告)号：US20110013608A1

公开(公告)日：2011-01-20

申请号：US12787515

申请日：2010-05-26

Applicant: Hee Jin LEE ,  Yong Hyu Kim ,  Seong II Hahm ,  Chong Kwon Kim

Inventor： Hee Jin LEE ,  Yong Hyu Kim ,  Seong II Hahm ,  Chong Kwon Kim

IPC: H04W84/02

CPC classification number: H04W72/04 ,  H04W84/12 ,  H04W88/10

Abstract: The present invention relates to a WLAN virtualization system which is capable of efficiently separating a Basic Service Set (BSS) into a plurality of virtual BSSs in a Time Division Multiplexing (TDM) manner. The WLAN virtualization system includes an Access Point (AP) for providing a plurality of vBSSs, and a plurality of stations corresponding to the vBSSs provided by the AP. Each of the vBSSs is operated on a superframe basis, the superframe being scheduled by a beacon frame transmitted from the AP. The superframe includes the beacon frame, one contention-free period, and one contention period. The CPs of the vBSSs include intervals which do not overlap each other. The vBSSs can be classified into any groups designated by a service provider based on certain criteria such as physical layer, QoS, security level, or network access authority, and times can be allocated to superframes at different rates or frequencies.

Abstract translation: 本发明涉及一种WLAN虚拟化系统，其能够以时分复用（TDM）方式有效地将基本业务集（BSS）分离成多个虚拟BSS。 WLAN虚拟化系统包括用于提供多个vBSS的接入点（AP）和对应于由AP提供的vBSS的多个站。 每个vBSS以超帧为基础进行操作，该超帧由从AP发送的信标帧进行调度。 超帧包括信标帧，一个争用周期和一个争用期。 vBSS的CP包括彼此不重叠的间隔。 可以根据诸如物理层，QoS，安全级别或网络访问权限等特定标准将vBSS分类为由服务提供商指定的任何组，并且可以将时间分配给不同速率或频率的超帧。

公开(公告)号：US20100181887A1

公开(公告)日：2010-07-22

申请号：US12691156

申请日：2010-01-21

Applicant: Joong-Hyun BAEK ,  Hee-Jin LEE

Inventor： Joong-Hyun BAEK ,  Hee-Jin LEE

IPC: H01J1/02

CPC classification number: H01L33/647 ,  G02B6/0023 ,  H01L33/62 ,  H01L33/642 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/01066 ,  H01L2924/00014

Abstract: A light emitting device with improved heat dissipation is provided. The light emitting device includes a first lead frame, a second lead frame, a light emitting element and a housing. The first lead frame includes a light emitting element mounting portion, a first heat dissipation portion extending from the light emitting element mounting portion in a first direction, and second and third heat dissipation portions extending from the light emitting element mounting portion in a second direction opposite to the first direction. The second lead frame extends in the second direction and is disposed between and spaced apart from the second and third heat dissipation portions. The light emitting element is mounted on the light emitting element mounting portion and is electrically coupled to the first and second lead frames. The housing encapsulates the first and second lead frames. The second and third heat dissipation portions have a first width and the second lead frame has a second width the same as or different from the first width.

Abstract translation: 提供了具有改善的散热的发光装置。 发光器件包括第一引线框架，第二引线框架，发光元件和壳体。 第一引线框架包括发光元件安装部分，从第一方向从发光元件安装部分延伸的第一散热部分和从发光元件安装部分沿相反的第二方向延伸的第二和第三散热部分 到第一个方向。 第二引线框架沿第二方向延伸并且设置在第二和第三散热部分之间并与第二和第三散热部分间隔开。 发光元件安装在发光元件安装部分上并且电耦合到第一引线框架和第二引线框架。 壳体封装第一和第二引线框架。 第二和第三散热部分具有第一宽度，第二引线框架具有与第一宽度相同或不同的第二宽度。

公开(公告)号：US20080141933A1

公开(公告)日：2008-06-19

申请号：US11984402

申请日：2007-11-16

Applicant: Cha-jea Jo ,  Joong-hyun Baek ,  Hee-jin Lee ,  Ku-young Kim ,  Ju-il Choi

Inventor： Cha-jea Jo ,  Joong-hyun Baek ,  Hee-jin Lee ,  Ku-young Kim ,  Ju-il Choi

IPC: B05C5/00

CPC classification number: C25D5/08 ,  C25D7/123 ,  C25D17/001 ,  C25D21/10 ,  H01L21/2885

Abstract: Provided is a semiconductor plating system for plating a semiconductor object with a desired layer. The semiconductor plating system include a plating tank configured to accommodate a plating solution for use in plating the semiconductor object, and a plating solution induction device configured to induce the plating solution to spirally flow toward the semiconductor object.

Abstract translation: 提供了一种用于对具有期望层的半导体物体进行电镀的半导体电镀系统。 半导体电镀系统包括：电镀槽，其配置为容纳用于电镀半导体物体的电镀液;以及电镀液感应装置，其被配置为使电镀液向半导体物体螺旋状流动。

公开(公告)号：US20070252271A1

公开(公告)日：2007-11-01

申请号：US11740821

申请日：2007-04-26

Applicant: Joong-Hyun BAEK ,  Sun-Won KANG ,  Moon-Jung KIM ,  Hyung-Gil BAEK ,  Hee-Jin LEE

Inventor： Joong-Hyun BAEK ,  Sun-Won KANG ,  Moon-Jung KIM ,  Hyung-Gil BAEK ,  Hee-Jin LEE

IPC: H01L23/34

CPC classification number: H01L25/16 ,  G11C5/04 ,  H01L21/563 ,  H01L25/0655 ,  H01L2224/73203 ,  H05K1/181 ,  H05K2201/09409 ,  H05K2201/09418 ,  H05K2201/10159 ,  Y02P70/611

Abstract: Provided is a semiconductor memory module allowing a filling member formed between a module substrate and memory chips mounted on the module substrate to completely fill the space between the module substrate and the memory chips. According to embodiments of the present invention, the semiconductor memory module includes a module substrate having at least one memory chip mounted on the substrate such that its edges are oblique to major and minor axes bisecting the module substrate. The oblique orientation allows for an improved opening between memory chips formed on the substrate so that the filling member may be properly formed between the module substrate and the memory chips to prevent voids where the filling member is not formed.

Abstract translation: 提供了一种半导体存储器模块，其允许形成在模块基板和安装在模块基板上的存储芯片之间的填充构件完全填充模块基板和存储器芯片之间的空间。 根据本发明的实施例，半导体存储器模块包括具有安装在基板上的至少一个存储芯片的模块基板，使得其边缘对于将模块基板平分的主轴和短轴倾斜。 倾斜方向允许在基板上形成的存储芯片之间的开口改善，使得填充构件可以适当地形成在模块基板和存储芯片之间，以防止填充构件未形成的空隙。

公开(公告)号：US06701371B1

公开(公告)日：2004-03-02

申请号：US09385099

申请日：1999-08-30

Applicant: Hee-jin Lee

Inventor： Hee-jin Lee

IPC: G06F1516

CPC classification number: H04L12/40097 ,  H04L12/6418 ,  H04L29/06 ,  H04L29/06027 ,  H04L47/193 ,  H04L47/2441 ,  H04L69/16 ,  H04L69/168 ,  H04L69/32

Abstract: A data transfer method for matching an upper protocol layer to a high speed serial bus. In the data transfer method, it is determined whether transfer data to be transferred from the upper protocol layer to the high speed serial bus, is stream data that is transferred to a predetermined node which the bus can identify, and form data flow defined by a predetermined flow classifier. If the transfer data is determined to be stream data, a channel is allocated in the bus and the transfer data is transferred through the channel. However, if the transfer data is determined not to be stream data, the transfer data is transferred by an asynchronous transfer method according to the high speed serial bus standard, without allocating a channel. Due to a channel Matron of the high speed serial bus, an upper protocol layer of existing applications which do not specify a service to provide, can be effectively matched to the high speed serial bus.

Abstract translation: 一种用于将上层协议层与高速串行总线进行匹配的数据传输方法。 在数据传送方法中，确定要从上层协议层传送到高速串行总线的传送数据是否被传送到总线可以识别的预定节点的流数据，并形成由 预定流分类器。 如果传输数据被确定为流数据，则在总线中分配信道，并且通过信道传送传输数据。 然而，如果确定传输数据不是流数据，则不需要分配信道就可以通过异步传输方法根据高速串行总线标准传送传输数据。 由于高速串行总线的通道Matron，没有规定提供服务的现有应用的上层协议层可以有效地匹配高速串行总线。

公开(公告)号：US06542506B1

公开(公告)日：2003-04-01

申请号：US09375566

申请日：1999-08-17

Applicant: Hee-Jin Lee

Inventor： Hee-Jin Lee

IPC: H04L1256

CPC classification number: H04L12/40058 ,  H04L12/40065 ,  H04L12/40071 ,  H04L12/40097 ,  H04L12/46 ,  H04L45/00 ,  H04L49/107 ,  H04L69/16 ,  H04L69/161 ,  H04L69/166 ,  H04L69/168 ,  H04L69/169 ,  H04L2012/5618 ,  H04L2012/5621 ,  H04L2012/5626 ,  H04L2012/5667 ,  H04Q11/0478

Abstract: A method of transferring data between networks includes storing a connection path set between predetermined data from a first network and a predetermined address in a second network during initial connection between the first and second networks, and transferring the predetermined data from the first network along the stored path. Accordingly, data transmission speed is faster by pre-mapping a data path between networks, and hardware and software loads on the gateway for repeating data between networks can be reduced.

Abstract translation: 在网络之间传送数据的方法包括在第一和第二网络之间的初始连接期间存储在第一网络的预定数据与第二网络中的预定地址之间设置的连接路径，以及沿着存储的第一网络从第一网络传送预定数据 路径。 因此，通过预先映射网络之间的数据路径，数据传输速度更快，并且可以减少网关上用于在网络之间重复数据的硬件和软件负载。

公开(公告)号：US08524539B2

公开(公告)日：2013-09-03

申请号：US13210607

申请日：2011-08-16

Applicant: Hee-Jin Lee ,  Joong-Hyun Baek

Inventor： Hee-Jin Lee ,  Joong-Hyun Baek

IPC: H01L21/00

CPC classification number: H01L23/4334 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/3677 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02166 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/0615 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/06519 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48647 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Provided are a semiconductor package of a semiconductor chip, a semiconductor module, an electronic system, and methods of manufacturing the same. The method includes mounting a semiconductor chip on a package substrate, forming a molding member on the semiconductor chip, forming via holes penetrating the molding member to expose a portion of a top surface of the semiconductor chip, the via holes being arranged in a lattice shape in a plan view, and forming thermally conductive via plugs in the via holes.

Abstract translation: 提供半导体芯片，半导体模块，电子系统的半导体封装及其制造方法。 该方法包括将半导体芯片安装在封装基板上，在半导体芯片上形成模制构件，形成穿过模制构件的通孔以暴露半导体芯片的顶表面的一部分，通孔布置成格子状 并且在通孔中通过塞子形成热传导。

公开(公告)号：US20130106889A1

公开(公告)日：2013-05-02

申请号：US13615395

申请日：2012-09-13

Applicant: Hee Jin LEE ,  Young Gwan KIM ,  You Sub JUNG ,  Jong-Hun HAN

Inventor： Hee Jin LEE ,  Young Gwan KIM ,  You Sub JUNG ,  Jong-Hun HAN

IPC: G09G5/00

CPC classification number: G06T1/60 ,  G06T15/005 ,  G06T15/04

Abstract: A graphics processing method and devices using the same is provided. The method includes receiving a plurality of texels arranged in a tiled format and rearranging, by a graphics processing unit (GPU), texels into a sequential format. In a tiled format, texels may be arranged in tiles, at least one tile including M×N texels. In the sequential format, the texels may be arranged in a scan line order of a display.

Abstract translation: 提供图形处理方法和使用其的装置。 该方法包括接收以平铺格式排列的多个纹素，并由图形处理单元（GPU）重新排列，将其细分为顺序格式。 在平铺格式中，纹理可以被布置在瓦片中，至少一个瓦片包括M×N个纹素。 在顺序格式中，纹理可以以显示器的扫描线顺序排列。