公开(公告)号：US06451705B1

公开(公告)日：2002-09-17

申请号：US09653522

申请日：2000-08-31

申请人： Shane J. Trapp ,  Kevin G. Donohoe

发明人： Shane J. Trapp ,  Kevin G. Donohoe

IPC分类号： H01L2100

CPC分类号： H01L21/76224 ,  H01L21/0271 ,  H01L21/3086 ,  Y10T428/24537

摘要： A method for forming an etched feature in a substrate such as an insulator layer of a semiconductor wafer is provided. In one embodiment, the method includes initially etching a substrate layer using a photoresist or other masking layer to form the etched feature (e.g., opening) to a selected depth, and depositing a self-aligning mask layer for a continued etch of the formed feature. In another embodiment of the method, the self-aligned mask is deposited onto a substrate having an etched opening or other feature, to protect the upper surface and corners of the substrate and sidewalls of the feature while the bottom portion of the opening is cleaned or material at the bottom portion of the opening is removed. The present methods utilize the height difference between the bottom portion of the feature and the surface of the substrate to selectively deposit a self-aligning mask layer relative to a pre-formed opening or other feature, for example, to extend an opening to a depth that an original photomask thickness cannot support.

摘要翻译： 提供了一种在诸如半导体晶片的绝缘体层的衬底中形成蚀刻特征的方法。 在一个实施例中，该方法包括首先使用光致抗蚀剂或其它掩模层来蚀刻衬底层，以形成到所选深度的蚀刻特征（例如，打开），以及沉积自对准掩模层以用于对形成的特征的连续蚀刻 。 在该方法的另一实施例中，将自对准掩模沉积到具有蚀刻开口或其他特征的基底上，以保护基底的上表面和角部以及特征的侧壁，同时清洁开口的底部部分 去除开口底部的材料。 本方法利用特征的底部与基底的表面之间的高度差，相对于预先形成的开口或其他特征选择性地沉积自对准掩模层，例如将开口延伸至深度 原始的光掩模厚度不能支持。

公开(公告)号：US06630410B2

公开(公告)日：2003-10-07

申请号：US10217719

申请日：2002-08-13

申请人： Shane J. Trapp ,  Kevin G. Donohoe

发明人： Shane J. Trapp ,  Kevin G. Donohoe

IPC分类号： H01L2100

CPC分类号： H01L21/76224 ,  H01L21/0271 ,  H01L21/3086 ,  Y10T428/24537

摘要： A method for forming an etched feature in a substrate such as an insulator layer of a semiconductor wafer is provided. In one embodiment, the method includes initially etching a substrate layer using a photoresist or other masking layer to form the etched feature (e.g., opening) to a selected depth, and depositing a self-aligning mask layer for a continued etch of the formed feature. In another embodiment of the method, the self-aligned mask is deposited onto a substrate having an etched opening or other feature, to protect the upper surface and corners of the substrate and sidewalls of the feature while the bottom portion of the opening is cleaned or material at the bottom portion of the opening is removed. The present methods utilize the height difference between the bottom portion of the feature and the surface of the substrate to selectively deposit a self-aligning mask layer relative to a pre-formed opening or other feature, for example, to extend an opening to a depth that an original photomask thickness cannot support.

公开(公告)号：US20110250759A1

公开(公告)日：2011-10-13

申请号：US13164970

申请日：2011-06-21

申请人： Gurtej S. Sandhu ,  Max F. Hineman ,  Daniel A. Steckert ,  Jingyi Bai ,  Shane J. Trapp ,  Tony Schrock

发明人： Gurtej S. Sandhu ,  Max F. Hineman ,  Daniel A. Steckert ,  Jingyi Bai ,  Shane J. Trapp ,  Tony Schrock

IPC分类号： H01L21/3065

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  Y10S438/906

摘要： A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.

摘要翻译： 描述了使用硬光致抗蚀剂掩模的高纵横比接触蚀刻氧化物层中的基本上垂直的接触孔的方法。 氧化物层沉积在下面的衬底上。 由碳源气体形成等离子体蚀刻气体。 掺杂剂混入气体中。 掺杂的等离子体蚀刻气体通过在蚀刻工艺期间将沿着接触孔的侧壁形成的碳链聚合物掺杂到导电状态来蚀刻通过氧化物层的基本垂直的接触孔。 碳链聚合物的导电状态减少了沿着侧壁的电荷累积，以防止通过渗出电荷并确保与有源区着陆区域的适当对准来接合孔的扭曲。 蚀刻停止在下面的基底。

公开(公告)号：US06569774B1

公开(公告)日：2003-05-27

申请号：US09652835

申请日：2000-08-31

申请人： Shane J. Trapp

发明人： Shane J. Trapp

IPC分类号： H01L21302

CPC分类号： H01L21/31116 ,  H01L21/31144

摘要： A plasma etch process for forming a high aspect ratio contact opening through a silicon oxide layer is disclosed. The silicon oxide layer is plasma etched using etch gases that include at least one organic fluorocarbon gas. At least one etch gas is used that includes one or more nitrogen-comprising gases to deposit a surface polymeric material during the etching for maintaining a masking layer over the silicon oxide layer. The method of the invention achieves a complete and anistropic etching of a contact opening having a high aspect ratio and the desired dimensions.

摘要翻译： 公开了一种通过氧化硅层形成高纵横比接触开口的等离子体蚀刻工艺。 使用包括至少一种有机碳氟化合物气体的蚀刻气体等离子体蚀刻氧化硅层。 在蚀刻期间使用至少一种蚀刻气体，其包括一种或多种含氮气体以沉积表面聚合材料，以在氧化硅层上保持掩模层。 本发明的方法实现了具有高纵横比和所需尺寸的接触开口的完全和无痛蚀刻。

公开(公告)号：US07419913B2

公开(公告)日：2008-09-02

申请号：US11217905

申请日：2005-09-01

申请人： Thomas M. Graettinger ,  John K. Zahurak ,  Shane J. Trapp ,  Thomas Arthur Figura

发明人： Thomas M. Graettinger ,  John K. Zahurak ,  Shane J. Trapp ,  Thomas Arthur Figura

IPC分类号： H01L21/461

CPC分类号： H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76844 ,  H01L27/10852

摘要： This invention includes methods of forming openings into dielectric material. In one implementation, an opening is partially etched through dielectric material, with such opening comprising a lowest point and opposing sidewalls of the dielectric material. At least respective portions of the opposing sidewalls within the opening are lined with an electrically conductive material. With such electrically conductive material over said respective portions within the opening, plasma etching is conducted into and through the lowest point of the dielectric material of the opening to extend the opening deeper within the dielectric material. Other aspects and implementations are contemplated.

摘要翻译： 本发明包括在电介质材料中形成开口的方法。 在一个实施方案中，通过电介质材料部分蚀刻开口，其中这种开口包括介电材料的最低点和相对的侧壁。 开口内的相对侧壁的至少相应部分衬有导电材料。 通过在开口内的所述各个部分上的这种导电材料，等离子体蚀刻被导入并通过开口的电介质材料的最低点，以使电介质材料内的开口更深。 考虑了其他方面和实现。

公开(公告)号：US07291895B2

公开(公告)日：2007-11-06

申请号：US10391952

申请日：2003-03-18

申请人： Shane J. Trapp ,  Brian F. Lawlor

发明人： Shane J. Trapp ,  Brian F. Lawlor

IPC分类号： H01L29/12

CPC分类号： H01L29/6656 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02321 ,  H01L21/02351 ,  H01L21/3081 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/31608 ,  H01L21/3185 ,  H01L21/76897 ,  H01L21/823468 ,  H01L21/823475 ,  Y10S257/90

摘要： A silicon nitride comprising layer formed over a semiconductor substrate includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate thereto. The silicon dioxide comprising layer is removed substantially selectively relative to the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the removal. A substantially undoped silicon dioxide comprising layer formed over a semiconductor substrate includes B, Al, Ga or mixtures thereof. A doped silicon dioxide comprising layer is formed proximate thereto. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer, with the B, Al, Ga or mixtures thereof enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removal. Integrated circuitry is also disclosed.

摘要翻译： 在半导体衬底上形成的包含氮化硅的层包括Al，Ga或它们的混合物。 包含二氧化硅的层在其附近形成。 相对于含氮化硅的层，基本上选择性地除去含二氧化硅的层，其中Al，Ga或其混合物在去除期间增强对包含氮化硅的层的选择性。 形成在半导体衬底上的基本上未掺杂的二氧化硅包括B，Al，Ga或其混合物。 在其附近形成掺杂二氧化硅的层。 基本上选择性地相对于基本上未掺杂的含二氧化硅的层去除掺杂的二氧化硅层，其中B，Al，Ga或其混合物在去除期间增强对基本上未掺杂的含二氧化硅的层的选择性。 还公开了集成电路。

公开(公告)号：US07202171B2

公开(公告)日：2007-04-10

申请号：US09752685

申请日：2001-01-03

申请人： Shane J. Trapp

发明人： Shane J. Trapp

IPC分类号： H01L21/311

CPC分类号： H01L21/76831 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76897

摘要： A method of forming a self-aligned contact opening in an insulative layer formed over a substrate in a semiconductor device involves etching the insulative layer with at least one fluorocarbon and ammonia.

摘要翻译： 在半导体器件中在衬底上形成的绝缘层中形成自对准接触开口的方法包括用至少一种碳氟化合物和氨蚀刻绝缘层。

公开(公告)号：US06897120B2

公开(公告)日：2005-05-24

申请号：US09920978

申请日：2001-08-01

申请人： Shane J. Trapp

发明人： Shane J. Trapp

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/762 ,  H01L21/76 ,  H01L21/312

CPC分类号： H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76224

摘要： A method of forming integrated circuitry includes forming a silicon nitride comprising layer over a semiconductor substrate. At least a portion of the silicon nitride comprising layer is etched using an etching chemistry comprising ammonia and at least one fluorocarbon. A method of forming shallow trench isolation in a semiconductor substrate includes depositing a silicon nitride comprising layer over a bulk semiconductor substrate. A photoresist comprising masking layer is formed over the silicon nitride comprising layer. The photoresist comprising masking layer is patterned effective to form a plurality of shallow trench mask openings therethrough. The silicon nitride comprising layer is etched through the mask openings substantially selectively relative to the photoresist using an etching chemistry comprising ammonia and at least one fluorocarbon.

摘要翻译： 形成集成电路的方法包括在半导体衬底上形成含氮化硅的层。 使用包含氨和至少一种碳氟化合物的蚀刻化学品蚀刻至少一部分氮化硅包覆层。 在半导体衬底中形成浅沟槽隔离的方法包括在体半导体衬底上沉积包含氮化硅的层。 包含掩模层的光致抗蚀剂形成在氮化硅包覆层上。 包含掩模层的光致抗蚀剂被图形化以形成多个通过其中的浅沟槽掩模开口。 使用包含氨和至少一种碳氟化合物的蚀刻化学品，相对于光致抗蚀剂，基本上选择性地通过掩模开口蚀刻含氮化硅的层。

公开(公告)号：US06806197B2

公开(公告)日：2004-10-19

申请号：US09924816

申请日：2001-08-07

申请人： Shane J. Trapp ,  Brian F. Lawlor

发明人： Shane J. Trapp ,  Brian F. Lawlor

IPC分类号： H01L21302

CPC分类号： H01L29/6656 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02321 ,  H01L21/02351 ,  H01L21/3081 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/31608 ,  H01L21/3185 ,  H01L21/76897 ,  H01L21/823468 ,  H01L21/823475 ,  Y10S257/90

摘要： A silicon nitride comprising layer formed over a semiconductor substrate includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate thereto. The silicon dioxide comprising layer is removed substantially selectively relative to the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the removal. A substantially undoped silicon dioxide comprising layer formed over a semiconductor substrate includes B, Al, Ga or mixtures thereof. A doped silicon dioxide comprising layer is formed proximate thereto. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer, with the B, Al, Ga or mixtures thereof enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removal. Integrated circuitry is also disclosed.

摘要翻译： 在半导体衬底上形成的包含氮化硅的层包括Al，Ga或它们的混合物。 包含二氧化硅的层在其附近形成。 相对于含氮化硅的层，基本上选择性地除去含二氧化硅的层，其中Al，Ga或其混合物在去除期间增强对包含氮化硅的层的选择性。 形成在半导体衬底上的基本上未掺杂的二氧化硅包括B，Al，Ga或其混合物。 在其附近形成掺杂二氧化硅的层。 基本上选择性地相对于基本上未掺杂的含二氧化硅的层去除掺杂的二氧化硅层，其中B，Al，Ga或其混合物在去除期间增强对基本上未掺杂的含二氧化硅的层的选择性。 还公开了集成电路。

公开(公告)号：US08673787B2

公开(公告)日：2014-03-18

申请号：US13164970

申请日：2011-06-21

申请人： Gurtej S. Sandhu ,  Max F. Hineman ,  Daniel A. Steckert ,  Jingyi Bai ,  Shane J. Trapp ,  Tony Schrock

发明人： Gurtej S. Sandhu ,  Max F. Hineman ,  Daniel A. Steckert ,  Jingyi Bai ,  Shane J. Trapp ,  Tony Schrock

IPC分类号： H01L21/302

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  Y10S438/906

摘要： A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.

摘要翻译： 描述了使用硬光致抗蚀剂掩模的高纵横比接触蚀刻氧化物层中的基本上垂直的接触孔的方法。 氧化物层沉积在下面的衬底上。 由碳源气体形成等离子体蚀刻气体。 掺杂剂混入气体中。 掺杂的等离子体蚀刻气体通过将在蚀刻过程中沿着接触孔的侧壁形成的碳链聚合物掺杂到导电状态来蚀刻通过氧化物层的基本垂直的接触孔。 碳链聚合物的导电状态减少了沿着侧壁的电荷累积，以防止通过渗出电荷并确保与有源区着陆区域的适当对准来接合孔的扭曲。 蚀刻停止在下面的基底。