公开(公告)号：US4853760A

公开(公告)日：1989-08-01

申请号：US89959

申请日：1987-08-25

申请人： Masahiro Abe ,  Masaharu Aoyama ,  Jiro Ohshima ,  Takashi Ajima

发明人： Masahiro Abe ,  Masaharu Aoyama ,  Jiro Ohshima ,  Takashi Ajima

IPC分类号： H01L21/768 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/312 ,  H01L23/522

CPC分类号： H01L21/3105 ,  H01L21/31155 ,  H01L2924/0002

摘要： A semiconductor device has a passivation layer including a polyimide film. Argon ions are implanted in the polyimide film to convert it into an electrically stable insulating film.

摘要翻译： 半导体器件具有包括聚酰亚胺膜的钝化层。 将氩离子注入到聚酰亚胺膜中以将其转化为电稳定的绝缘膜。

公开(公告)号：US4404736A

公开(公告)日：1983-09-20

申请号：US319411

申请日：1981-11-09

申请人： Yutaka Koshino ,  Takashi Ajima ,  Jiro Ohshima ,  Masahiro Abe

发明人： Yutaka Koshino ,  Takashi Ajima ,  Jiro Ohshima ,  Masahiro Abe

IPC分类号： H01L21/316 ,  H01L23/29 ,  H01L23/31

CPC分类号： H01L23/3171 ,  H01L21/316 ,  H01L23/291 ,  H01L23/3178 ,  H01L2924/0002 ,  H01L2924/3511 ,  Y10S148/05 ,  Y10S148/085 ,  Y10S148/159 ,  Y10S438/928

摘要： A method for manufacturing a semiconductor device of mesa type comprises forming mesa recesses of predetermined depth around an element in the surface of a semiconductor body, forming on the back of semiconductor body a film for lessening the concentration of stress, filling glass powder into mesa recesses, and sintering glass powder to form glass insulators. According to the method of the present invention, cracks can be prevented from being caused in the semiconductor body and glass insulators formed in mesa recesses.

摘要翻译： 一种台面型半导体器件的制造方法包括在半导体本体的表面的元件周围形成预定深度的台面凹部，在半导体本体的背面形成用于减小应力集中的膜，将玻璃粉末填充到台面凹部 ，并烧结玻璃粉末以形成玻璃绝缘体。 根据本发明的方法，可以防止在形成在台面凹部中的半导体本体和玻璃绝缘体中产生裂纹。

公开(公告)号：US4520041A

公开(公告)日：1985-05-28

申请号：US548440

申请日：1983-11-03

申请人： Masaharu Aoyama ,  Masahiro Abe ,  Takashi Ajima ,  Toshio Yonezawa

发明人： Masaharu Aoyama ,  Masahiro Abe ,  Takashi Ajima ,  Toshio Yonezawa

IPC分类号： H01L21/3205 ,  H01L21/306 ,  H01L21/768 ,  H01L23/532 ,  H01L21/283 ,  H01L21/302

CPC分类号： H01L23/53295 ,  H01L21/7684 ,  H01L23/5329 ,  H01L2924/0002

摘要： A metallization structure having a substantially flat surface can be formed on a semiconductor substrate by forming first and second insulating layers on the substrate. The second insulating layer is selectively removed to form grooves therein. Then, a metallic material layer is conformably formed. The metallic layer has grooves corresponding to the grooves of the second insulating layer. A flowable polymer is applied to the surface of the resultant structure to form a layer having a flat surface. The polymer layer and the metallic layer are sequentially ion-etched to expose the second insulating layer. Thus, the metallization structure constituted by the remaining metallic layer and the second insulating layer is formed to have a flat surface.

摘要翻译： 通过在衬底上形成第一绝缘层和第二绝缘层，可以在半导体衬底上形成具有基本平坦表面的金属化结构。 选择性地去除第二绝缘层以在其中形成凹槽。 然后，顺应地形成金属材料层。 金属层具有与第二绝缘层的槽对应的槽。 将可流动的聚合物施加到所得结构的表面以形成具有平坦表面的层。 依次离子蚀刻聚合物层和金属层以露出第二绝缘层。 因此，由剩余的金属层和第二绝缘层构成的金属化结构形成为具有平坦的表面。

公开(公告)号：US4636832A

公开(公告)日：1987-01-13

申请号：US837663

申请日：1986-03-04

申请人： Masahiro Abe ,  Masaharu Aoyama ,  Takashi Ajima ,  Toshio Yonezawa

发明人： Masahiro Abe ,  Masaharu Aoyama ,  Takashi Ajima ,  Toshio Yonezawa

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/532 ,  H01L23/14

CPC分类号： H01L24/85 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/85 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12036 ,  H01L2924/19043 ,  H01L2924/20752

摘要： A semiconductor device with a bonding section comprising a semiconductor substrate, a silicon layer formed on the semiconductor substrate with a first insulating layer interposed therebetween, and a bonding pad formed on the silicon layer with a second insulating layer interposed therebetween. The silicon layer has substantially the same size as the bonding pad. When a lead line is bonded to the bonding pad, the silicon layer lessens the stress caused by the bonding.

摘要翻译： 一种具有接合部分的半导体器件，包括半导体衬底，在半导体衬底上形成有第一绝缘层的硅层，以及形成在硅层上并具有介于其间的第二绝缘层的接合焊盘。 硅层具有与焊盘大致相同的尺寸。 当引线与接合焊盘接合时，硅层减小由接合引起的应力。

公开(公告)号：US4613888A

公开(公告)日：1986-09-23

申请号：US634030

申请日：1984-07-24

申请人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama ,  Takashi Ajima

发明人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama ,  Takashi Ajima

IPC分类号： H01L21/768 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/316 ,  H01L23/532 ,  H01L21/44 ,  H01L21/47 ,  H01L21/94

CPC分类号： H01L23/5329 ,  H01L2924/0002

摘要： A semiconductor device is disclosed which includes a multilayer formed of a hard inorganic main insulation film and a soft subinsulation film as insulation interlayers, and a hard inorganic insulation film as a final passivation film. The final passivation film is directly deposited on the hard inorganic main insulation film of the multilayer.

摘要翻译： 公开了一种半导体器件，其包括由作为绝缘夹层的硬质无机主绝缘膜和软嵌层膜形成的多层，以及作为最终钝化膜的硬质无机绝缘膜。 最终的钝化膜直接沉积在多层的硬质无机主绝缘膜上。

公开(公告)号：US4618878A

公开(公告)日：1986-10-21

申请号：US621086

申请日：1984-06-15

申请人： Masaharu Aoyama ,  Masahiro Abe ,  Takashi Ajima ,  Toshio Yonezawa

发明人： Masaharu Aoyama ,  Masahiro Abe ,  Takashi Ajima ,  Toshio Yonezawa

IPC分类号： H01L21/768 ,  H01L21/31 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L23/5329 ,  H01L2924/0002

摘要： A semiconductor device having a multilayer wiring structure which comprises a semiconductor substrate, a first wiring layer deposited on said substrate, and a second wiring layer deposited on said first wiring layer with insulating layers disposed therebetween, wherein the insulating interlayer consists of an inorganic insulating layer and a polyimide-based resin film overlying the inorganic insulating layer. The thickness ratio of the polyimide-based resin film to the inorganic insulating film ranges from 0.1 to 0.5. A method of manufacturing a semiconductor device of a multilayer wiring structure wherein an opening is formed in the insulating interlayer to have a small step.

摘要翻译： 一种具有多层布线结构的半导体器件，包括半导体衬底，沉积在所述衬底上的第一布线层和沉积在所述第一布线层上的绝缘层的第二布线层，其中绝缘中间层由无机绝缘层 以及覆盖无机绝缘层的聚酰亚胺系树脂膜。 聚酰亚胺系树脂膜与无机绝缘膜的厚度比为0.1〜0.5。 一种制造多层布线结构的半导体器件的方法，其中在绝缘中间层中形成具有小台阶的开口。

公开(公告)号：US4462856A

公开(公告)日：1984-07-31

申请号：US467298

申请日：1983-02-17

申请人： Masahiro Abe ,  Toshio Yonezawa ,  Masaharu Aoyama ,  Takashi Ajima

发明人： Masahiro Abe ,  Toshio Yonezawa ,  Masaharu Aoyama ,  Takashi Ajima

IPC分类号： C23F1/00 ,  H01L21/306 ,  H01L21/3213 ,  C23F1/02 ,  C25F3/04 ,  C25F3/12

CPC分类号： C23F1/00 ,  H01L21/306 ,  H01L21/32134

摘要： A system is adapted to etch an aluminium film on a semiconductor wafer into a predetermined pattern by immersing the film in an etching solution. The system comprises a voltage detecting circuit for detecting a voltage created between a platinum electrode and the aluminium film on the semiconductor wafer which are immersed in the etching solution, a comparator for comparing a reference voltage with the voltage detected by the voltage detecting circuit to produce an output signal, and a timer for starting a time count operation upon receipt of the output signal from the comparator and for producing an etching completion signal when it continuously receives the output signal from the comparator for a predetermined time period.

摘要翻译： 系统适于通过将膜浸入蚀刻溶液中将半导体晶片上的铝膜蚀刻成预定图案。 该系统包括电压检测电路，用于检测浸在蚀刻溶液中的铂电极和半导体晶片上的铝膜之间产生的电压;比较器，用于将参考电压与由电压检测电路检测到的电压进行比较，以产生 输出信号，以及在从比较器接收到输出信号时开始时间计数操作的定时器，并且当其在预定时间段内连续接收来自比较器的输出信号时产生蚀刻完成信号。

公开(公告)号：US4426234A

公开(公告)日：1984-01-17

申请号：US327190

申请日：1981-12-03

申请人： Jiro Ohshima ,  Yutaka Koshino ,  Takashi Ajima ,  Toshio Yonezawa

发明人： Jiro Ohshima ,  Yutaka Koshino ,  Takashi Ajima ,  Toshio Yonezawa

IPC分类号： H01L21/225 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/425 ,  H01L21/74

CPC分类号： H01L21/31155 ,  H01L21/2255 ,  H01L21/265

摘要： The invention discloses a method for fabricating a semiconductor device comprising the steps of: forming, on an entire surface of a semiconductor substrate of one conductivity type, a first thin film of a diffusion coefficient greater than a diffusion coefficient of the substrate; forming, on an entire surface of the first thin film, a second thin film having a diffusion coefficient smaller than the diffusion coefficient of the first thin film; ion-implanting an impurity through the second thin film into the first thin film to form an impurity region, said impurity having a conductivity type opposite to the conductivity type of the substrate; and effecting annealing to set a junction depth of the impurity region to a predetermined value. According to the method of the invention, an impurity region having a desired sheet resistivity and a desired diffusion depth can be formed in the semiconductor substrate with excellent reproducibility and control. The formation of the lattice defect can be prevented and the carrier life time can be improved. Gallium is preferably used as the impurity according to the invention.

摘要翻译： 本发明公开了一种制造半导体器件的方法，包括以下步骤：在一个导电类型的半导体衬底的整个表面上形成大于衬底扩散系数的扩散系数的第一薄膜; 在所述第一薄膜的整个表面上形成扩散系数小于所述第一薄膜的扩散系数的第二薄膜; 将杂质通过第二薄膜离子注入到第一薄膜中以形成杂质区，所述杂质具有与衬底的导电类型相反的导电类型; 并进行退火以将杂质区域的结深度设定为预定值。 根据本发明的方法，可以在半导体衬底中形成具有期望的电阻率和期望的扩散深度的杂质区，具有优异的再现性和控制性。 可以防止晶格缺陷的形成，并且可以提高载体寿命。 优选使用镓作为本发明的杂质。

公开(公告)号：US4515642A

公开(公告)日：1985-05-07

申请号：US525484

申请日：1983-08-22

申请人： Takashi Ajima ,  Jiro Ohshima ,  Yutaka Koshino

发明人： Takashi Ajima ,  Jiro Ohshima ,  Yutaka Koshino

IPC分类号： H01L21/22 ,  H01L21/265 ,  H01L21/266 ,  H01L21/316

CPC分类号： H01L21/02178 ,  H01L21/02263 ,  H01L21/22 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/3162

摘要： In a method of producing a semiconductor device, an alumina layer is formed directly on a principal surface of a silicon substrate; aluminum and silicon are ion-implanted through the alumina layer into said substrate; and the substrate is thereafter annealed. The ion-implanted silicon yields better crystalline structure and increases the solid solubility limit of aluminum.

摘要翻译： 在制造半导体器件的方法中，氧化铝层直接形成在硅衬底的主表面上; 铝和硅通过氧化铝层离子注入到所述衬底中; 然后退火基板。 离子注入的硅产生更好的晶体结构并增加铝的固溶度极限。

公开(公告)号：US4479830A

公开(公告)日：1984-10-30

申请号：US462201

申请日：1983-01-31

申请人： Yutaka Koshino ,  Jiro Ohshima ,  Takashi Ajima ,  Toshio Yonezawa

发明人： Yutaka Koshino ,  Jiro Ohshima ,  Takashi Ajima ,  Toshio Yonezawa

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L23/544

CPC分类号： H01L23/544 ,  H01L21/2022 ,  H01L21/26506 ,  H01L21/2652 ,  H01L2223/54453 ,  H01L2924/0002

摘要： A method for manufacturing a semiconductor device is shown which includes a step of ion implanting an impurity into an impurity-region formation region of a semiconductor substrate. Before or after the ion implantation step, silicon ions are implanted in a dose of 1.times.10.sup.13 to 1.times.10.sup.15 /cm.sup.2 into the impurity-region formation region and then the silicon ions so implanted are subjected to an activation treatment to form an epitaxial grown protrusion on the surface of the substrate. The protrusion is used as an alignment mark in the subsequent mask alignment step for photolithography.

摘要翻译： 示出了制造半导体器件的方法，其包括将杂质离子注入到半导体衬底的杂质区形成区域中的步骤。 在离子注入步骤之前或之后，将硅离子以1×10 13至1×10 15 / cm 2的剂量注入杂质区形成区域，然后将如此注入的硅离子进行活化处理，以在表面上形成外延生长突起 的基底。 在随后的用于光刻的掩模对准步骤中，该突起用作对准标记。