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公开(公告)号：US20080110546A1
公开(公告)日：2008-05-15
申请号：US11892638
申请日：2007-08-24
申请人： Shoko Omizo , Atsushi Yoshimura , Mitsuhiro Nakao , Junya Sagara , Masayuki Dohi , Tatsuhiko Shirakawa
发明人： Shoko Omizo , Atsushi Yoshimura , Mitsuhiro Nakao , Junya Sagara , Masayuki Dohi , Tatsuhiko Shirakawa
CPC分类号： H01L21/67132 , B32B2038/1891 , Y10T29/49131 , Y10T29/49133 , Y10T29/53178 , Y10T29/53183 , Y10T156/16
摘要： An apparatus for manufacturing a semiconductor device, includes: a collet; an alignment stage; and a sheet feeding mechanism. The collet is configured to suck a surface of a semiconductor chip. The surface is on opposite side of a bonding surface to be bonded to a bonding target. The bonding surface is provided with a film-like adhesive layer. The collet includes a heater for heating the adhesive layer. The alignment stage is configured to support the semiconductor chip and to correct position of the semiconductor chip. The sheet feeding mechanism is configured to feed a release sheet onto the alignment stage.
摘要翻译： 一种半导体器件的制造装置，包括：夹头; 对准阶段 和送纸机构。 夹头构造成吸附半导体芯片的表面。 该表面位于与结合靶接合的接合面的相反侧。 接合表面设置有膜状粘合剂层。 夹头包括用于加热粘合剂层的加热器。 对准台被配置为支撑半导体芯片并校正半导体芯片的位置。 片材进给机构构造成将释放片材供给到对准台上。
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公开(公告)号：US07849897B2
公开(公告)日：2010-12-14
申请号：US11892638
申请日：2007-08-24
申请人： Shoko Omizo , Atsushi Yoshimura , Mitsuhiro Nakao , Junya Sagara , Masayuki Dohi , Tatsuhiko Shirakawa
发明人： Shoko Omizo , Atsushi Yoshimura , Mitsuhiro Nakao , Junya Sagara , Masayuki Dohi , Tatsuhiko Shirakawa
IPC分类号： B32B41/00
CPC分类号： H01L21/67132 , B32B2038/1891 , Y10T29/49131 , Y10T29/49133 , Y10T29/53178 , Y10T29/53183 , Y10T156/16
摘要： An apparatus for manufacturing a semiconductor device, includes: a collet; an alignment stage; and a sheet feeding mechanism. The collet is configured to suck a surface of a semiconductor chip. The surface is on opposite side of a bonding surface to be bonded to a bonding target. The bonding surface is provided with a film-like adhesive layer. The collet includes a heater for heating the adhesive layer. The alignment stage is configured to support the semiconductor chip and to correct position of the semiconductor chip. The sheet feeding mechanism is configured to feed a release sheet onto the alignment stage.
摘要翻译： 一种半导体器件的制造装置，包括：夹头; 对准阶段 和送纸机构。 夹头构造成吸附半导体芯片的表面。 该表面位于与结合靶接合的接合面的相反侧。 接合表面设置有膜状粘合剂层。 夹头包括用于加热粘合剂层的加热器。 对准台被配置为支撑半导体芯片并校正半导体芯片的位置。 片材进给机构构造成将释放片材供给到对准台上。
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公开(公告)号：US20080099532A1
公开(公告)日：2008-05-01
申请号：US11867307
申请日：2007-10-04
申请人： Mitsuhiro Nakao , Junya Sagara , Katsuhiro Ishida , Noboru Okane
发明人： Mitsuhiro Nakao , Junya Sagara , Katsuhiro Ishida , Noboru Okane
CPC分类号： B23K20/005 , H01L24/78 , H01L24/85 , H01L2224/78301 , H01L2224/786 , H01L2224/851 , H01L2224/85148 , H01L2224/85205 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01025 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2224/48 , H01L2224/45099 , H01L2224/05599 , H01L2924/00
摘要： A wire bonding apparatus comprising: a capillary configured to have inserted therethrough a wire; a damper provided above the capillary and able to clamp hold the wire; and a load sensor configured to measure load incurred on the wire.
摘要翻译： 一种引线接合装置，包括：毛细管，其被配置为插入其中; 设置在毛细管上方的阻尼器，能够夹紧电线; 以及负载传感器，其被配置为测量在所述电线上产生的负载。
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公开(公告)号：US08231046B2
公开(公告)日：2012-07-31
申请号：US12564276
申请日：2009-09-22
申请人： Mitsuhiro Nakao , Junya Sagara , Katsuhiro Ishida , Noboru Okane
发明人： Mitsuhiro Nakao , Junya Sagara , Katsuhiro Ishida , Noboru Okane
CPC分类号： B23K20/005 , H01L24/78 , H01L24/85 , H01L2224/78301 , H01L2224/786 , H01L2224/851 , H01L2224/85148 , H01L2224/85205 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01025 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2224/48 , H01L2224/45099 , H01L2224/05599 , H01L2924/00
摘要： A wire bonding method involves bonding a wire in order at a first bonding point and a second bonding point; raising a capillary, through which the wire is inserted, on the second bonding point; cutting the wire by closing a clamper provided above the capillary at a time when the capillary has reached a prescribed height; and measuring a load incurred on the wire at a time of cutting of the wire.
摘要翻译： 引线接合方法包括在第一接合点和第二接合点处按顺序接合线; 在所述第二接合点上升起所述电线插入的毛细管; 通过在毛细管达到规定高度的时候关闭设置在毛细管上方的夹持器来切断线; 并测量在切割线时在线上产生的负载。
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公开(公告)号：US20100181367A1
公开(公告)日：2010-07-22
申请号：US12564276
申请日：2009-09-22
申请人： Mitsuhiro Nakao , Junya Sagara , Katsuhiro Ishida , Noboru Okane
发明人： Mitsuhiro Nakao , Junya Sagara , Katsuhiro Ishida , Noboru Okane
CPC分类号： B23K20/005 , H01L24/78 , H01L24/85 , H01L2224/78301 , H01L2224/786 , H01L2224/851 , H01L2224/85148 , H01L2224/85205 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01025 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2224/48 , H01L2224/45099 , H01L2224/05599 , H01L2924/00
摘要： A wire bonding method involves bonding a wire in order at a first bonding point and a second bonding point; raising a capillary, through which the wire is inserted, on the second bonding point; cutting the wire by closing a clamper provided above the capillary at a time when the capillary has reached a prescribed height; and measuring a load incurred on the wire at a time of cutting of the wire
摘要翻译： 引线接合方法包括在第一接合点和第二接合点处按顺序接合线; 在所述第二接合点上升起所述电线插入的毛细管; 通过在毛细管达到规定高度的时候关闭设置在毛细管上方的夹持器来切断线; 并测量在切割线时在线上产生的负载
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公开(公告)号：US20070023875A1
公开(公告)日：2007-02-01
申请号：US11490116
申请日：2006-07-21
申请人： Noboru Okane , Ryoji Matsushima , Kazuhiro Yamamori , Junya Sagara , Yoshio Iizuka , Kuniyuki Oonishi , Atsushi Yoshimura
发明人： Noboru Okane , Ryoji Matsushima , Kazuhiro Yamamori , Junya Sagara , Yoshio Iizuka , Kuniyuki Oonishi , Atsushi Yoshimura
IPC分类号： H01L23/495
CPC分类号： H01L23/49575 , H01L24/32 , H01L24/48 , H01L24/83 , H01L2224/2919 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/83191 , H01L2224/8385 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/0665 , H01L2924/07802 , H01L2924/181 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a lead frame having an element mounting part and a lead part. A first semiconductor element and a second semiconductor element are sequentially stacked on a principal surface at least on one side of the element mounting part. An insulating resin layer serving as a second adhesive layer is filled between the first semiconductor element and the second semiconductor element. An element-side end portion of a first bonding wire connected to the first semiconductor element is buried in the insulating resin layer.
摘要翻译： 半导体封装包括具有元件安装部分和引线部分的引线框架。 第一半导体元件和第二半导体元件依次堆叠在元件安装部的至少一侧的主表面上。 用作第二粘合剂层的绝缘树脂层填充在第一半导体元件和第二半导体元件之间。 连接到第一半导体元件的第一接合线的元件侧端部埋设在绝缘树脂层中。
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7.发明申请Semiconductor device having semiconductor chips stacked and mounted thereon and manufacturing method thereof 有权具有堆叠并安装在其上的半导体芯片的半导体器件及其制造方法公开(公告)号：US20060175697A1
公开(公告)日：2006-08-10
申请号：US11344063
申请日：2006-02-01
申请人： Tetsuya Kurosawa , Junya Sagara
发明人： Tetsuya Kurosawa , Junya Sagara
CPC分类号： H01L25/0657 , H01L21/6836 , H01L23/481 , H01L24/27 , H01L24/29 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L25/50 , H01L29/0657 , H01L2221/68327 , H01L2221/6834 , H01L2224/0401 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2224/13144 , H01L2224/29012 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/83191 , H01L2224/83194 , H01L2224/838 , H01L2224/8592 , H01L2224/92247 , H01L2225/0651 , H01L2225/06517 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06582 , H01L2924/00014 , H01L2924/01005 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/10155 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2924/3512 , H01L2924/00012
摘要： Chips are stacked and mounted on a circuit board having external connection electrodes and mounted thereon by wire bonding. At least one of the chips stacked on the chip includes overhung portions each of which has a start point inside bonding pads, is made thinner in a direction towards the outer periphery to an end point reaching the side wall and forms a space used to accommodate ball bonding portions between the overhung portion and the main surface of the chip arranged in the lower stage on a backside corresponding in position to the bonding pads, and insulating members formed to cover the overhung portions and prevent bonding wires of the chip arranged in the lower stage from being brought into contact with the upper-stage chip.
摘要翻译： 芯片堆叠并安装在具有外部连接电极的电路板上并通过引线接合安装在其上。 堆叠在芯片上的芯片中的至少一个包括在接合焊盘内部具有起始点的悬垂部分，在朝向外周边的方向到达到侧壁的端点处形成较薄，并形成用于容纳球的空间 在布置在下层的芯片的悬臂部分和主表面之间的接合部分在与接合焊盘相对应的背面上形成绝缘部件，以及形成为覆盖悬臂部分的绝缘部件，并且防止布置在下部的芯片的接合线 不与上级芯片接触。
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8.发明申请METHOD FOR MANUFACTURING A STACKED SEMICONDUCTOR PACKAGE, AND STACKED SEMICONDUCTOR PACKAGE 审中-公开堆叠半导体封装和堆叠半导体封装的制造方法公开(公告)号：US20110163459A1
公开(公告)日：2011-07-07
申请号：US13051179
申请日：2011-03-18
申请人： Junya Sagara , Shinya Takyu , Tetsuya Kurosawa
发明人： Junya Sagara , Shinya Takyu , Tetsuya Kurosawa
IPC分类号： H01L23/52
CPC分类号： H01L25/0657 , H01L21/6835 , H01L24/24 , H01L24/82 , H01L2221/6834 , H01L2224/24051 , H01L2224/24145 , H01L2224/24226 , H01L2224/24998 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/76155 , H01L2224/82001 , H01L2224/82007 , H01L2224/82102 , H01L2225/06524 , H01L2225/06562 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/10157 , H01L2924/10253 , H01L2924/19041 , H01L2924/30105 , H01L2924/00
摘要： A method for manufacturing a stacked semiconductor package where a plurality of semiconductor chips are stacked on a substrate, including: forming insulating layers at portions of a wafer corresponding to sides of the plurality of semiconductor chips when the plurality of semiconductor chips are in the wafer; processing the wafer so as to obtain the plurality of semiconductor chips; subsequently stacking the plurality of semiconductor chips on the substrate such that the insulating layers formed at the sides of the plurality of semiconductor chips are respectively positioned at the same side as one another; and forming a wiring over the insulating layers formed at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips are electrically connected with the substrate.
摘要翻译： 一种叠层半导体封装的制造方法，其中多个半导体芯片堆叠在基板上，包括：当所述多个半导体芯片在所述晶片中时，在与所述多个半导体芯片的侧面对应的晶片的部分处形成绝缘层; 处理晶片以获得多个半导体芯片; 随后将多个半导体芯片堆叠在基板上，使得形成在多个半导体芯片的侧面的绝缘层分别位于彼此相同的一侧; 以及在形成在所述多个半导体芯片的侧面的绝缘层上形成布线，使得所述多个半导体芯片彼此电连接，并且所述多个半导体芯片中的一个或多个与所述基板电连接。
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公开(公告)号：US07569921B2
公开(公告)日：2009-08-04
申请号：US11398694
申请日：2006-04-06
申请人： Noboru Okane , Ryoji Matsushima , Kazuhiro Yamamori , Junya Sagara , Yoshio Iizuka , Kuniyuki Ohnishi
发明人： Noboru Okane , Ryoji Matsushima , Kazuhiro Yamamori , Junya Sagara , Yoshio Iizuka , Kuniyuki Ohnishi
IPC分类号： H01L23/02
CPC分类号： H01L23/49575 , H01L24/48 , H01L24/49 , H01L24/92 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48095 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/48475 , H01L2224/49113 , H01L2224/73265 , H01L2224/85051 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/181 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor device has a plurality of bare chips stacked on at least one of first and second main surfaces oppositely arranged on a support substrate, spacers arranged between two bare chips arranged adjacently in up and down direction among the plurality of bare chips, and inner leads which are arranged at both sides in a horizontal direction of the support substrate and are connected to pads of the bare chips via bonding wires, wherein the bonding wires which connect the pads of the bare chips at one end side of the spacers to the corresponding inner leads, are arranged not to contact the bare chip at the other end side of the same spacer.
摘要翻译： 半导体器件具有堆叠在与支撑基板相对布置的第一和第二主表面中的至少一个上的多个裸芯片，布置在多个裸芯片之间沿上下方向布置的两个裸芯片之间的间隔物和内引线 其布置在支撑基板的水平方向的两侧，并且通过接合线连接到裸芯片的焊盘，其中，将间隔件的一端侧的裸芯片的焊盘连接到相应的内部的接合线 引线被布置成不与相同间隔物的另一端侧的裸芯片接触。
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公开(公告)号：US20070023922A1
公开(公告)日：2007-02-01
申请号：US11490022
申请日：2006-07-21
申请人： Noboru Okane , Ryoji Matsushima , Kazuhiro Yamamori , Junya Sagara , Yoshio Iizuka , Kuniyuki Oonishi
发明人： Noboru Okane , Ryoji Matsushima , Kazuhiro Yamamori , Junya Sagara , Yoshio Iizuka , Kuniyuki Oonishi
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06555 , H01L2225/06572 , H01L2225/06575 , H01L2924/00014 , H01L2924/09701 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a circuit board having connection pads formed on a front and back surfaces, and a wiring network connected to these connection pads, as a package base. Metal bumps connected to at least part of the connection pads on the front and back surfaces via the wiring network are formed on the back surface of the circuit board as external connection terminals. One or a plurality of semiconductor elements electrically connected to the connection pad on the front surface side is or are mounted on a first element mounting part provided on the front surface side of the circuit board. One or plurality of semiconductor elements electrically connected to the connection pad on the back surface side is or are mounted on a second element mounting part provided on the back surface side of the circuit board.
摘要翻译： 半导体封装包括具有形成在前表面和后表面上的连接焊盘的电路板和连接到这些连接焊盘的布线网络作为封装基座。 通过布线网络连接到前表面和后表面上的连接焊盘的至少一部分的金属凸块形成在电路板的背面上作为外部连接端子。 电连接到前表面侧的连接焊盘的一个或多个半导体元件被安装在设置在电路板的前表面侧的第一元件安装部分上。 电连接到背面侧的连接焊盘的一个或多个半导体元件被安装在设置在电路板的背面侧的第二元件安装部上。
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