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公开(公告)号：US20200328142A1
公开(公告)日：2020-10-15
申请号：US16538286
申请日：2019-08-12
发明人： Don-Son Jiang , Nai-Hao Kao , Chih-Sheng Lin , Szu-Hsien Chen , Chih-Yuan Shih , Chia-Cheng Chen , Yu-Cheng Pai , Hsuan-Hao Mi
IPC分类号： H01L23/498 , H01L23/14 , H01L23/367 , H01L23/00 , H01L21/48
摘要： A package stack structure and a method for fabricating the same are provided. An electronic component is disposed on the topmost one of a plurality of organic material substrates, and no chip is disposed on the remaining organic material substrates. A predefined layer number of circuit layers are disposed in the organic material substrates, and distributes the thermal stress via the organic material substrates. Therefore, the bottommost one of the organic material substrates will not be separated from a circuit board due to CTE mismatch. Also a carrier component is provided.
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公开(公告)号：US20170309537A1
公开(公告)日：2017-10-26
申请号：US15648089
申请日：2017-07-12
发明人： Shih-Chao Chiu , Chun-Hsien Lin , Yu-Cheng Pai , Wei-Chung Hsiao , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
IPC分类号： H01L23/31 , H01L23/498 , H01L21/56 , H01L21/48
CPC分类号： H01L23/49861 , H01L21/4846 , H01L23/3128 , H01L23/49811 , H01L23/49827 , H01L2224/73204 , H01L2224/92125 , H01L2924/181 , H01L2924/00012
摘要： A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.
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公开(公告)号：US09716060B2
公开(公告)日：2017-07-25
申请号：US14692769
申请日：2015-04-22
发明人： Shih-Chao Chiu , Chun-Hsien Lin , Yu-Cheng Pai , Wei-Chung Hsiao , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
IPC分类号： H01L23/498 , H05K3/00 , H05K3/32 , H05K1/18 , H01L23/538 , H01L23/00 , H05K1/02 , H05K3/10 , H05K3/46 , H01L23/31 , H01L21/683
CPC分类号： H01L23/49838 , H01L21/6835 , H01L23/3121 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L2221/68318 , H01L2221/68345 , H01L2224/131 , H01L2224/13147 , H01L2224/16227 , H01L2224/16237 , H01L2224/26175 , H01L2224/2919 , H01L2224/32058 , H01L2224/32105 , H01L2224/32106 , H01L2224/32237 , H01L2224/73204 , H01L2224/81801 , H01L2224/83101 , H01L2924/15313 , H01L2924/18161 , H01L2924/19041 , H01L2924/19103 , H01L2924/19104 , H05K1/0231 , H05K1/185 , H05K1/186 , H05K1/189 , H05K3/0026 , H05K3/007 , H05K3/108 , H05K3/32 , H05K3/4682 , H05K2201/0376 , H05K2201/10515 , H05K2201/1053 , H05K2201/10674 , H05K2201/10977 , H01L2924/014 , H01L2924/00014 , H01L2924/0665
摘要： The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.
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4.发明申请公开(公告)号：US20160163621A1
公开(公告)日：2016-06-09
申请号：US14876404
申请日：2015-10-06
发明人： Shih-Chao Chiu , Chun-Hsien Lin , Yu-Cheng Pai , Wei-Chung Hsiao , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
IPC分类号： H01L23/498 , H01L21/56 , H01L23/31 , H01L21/48
CPC分类号： H01L23/49861 , H01L21/4846 , H01L23/3128 , H01L23/49811 , H01L23/49827 , H01L2224/73204 , H01L2224/92125 , H01L2924/181 , H01L2924/00012
摘要： A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.
摘要翻译： 提供一种单层布线封装基板及其制造方法，该方法包括：在载体上形成具有与第一表面相对并与载体接触的第一表面和第二表面的布线层; 在所述载体上和所述布线层上形成绝缘体，所述绝缘体具有第一侧面，所述第一侧面具有第一开口，所述布线层的一部分从该第一开口露出;以及与所述第一侧相对的第二侧， 布线层表面; 并且在绝缘体的第二面和布线层的第二表面露出的同时移除载体。 因此，制造无芯封装基板，并且减小基板的整体厚度和成本。
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公开(公告)号：US20160081186A1
公开(公告)日：2016-03-17
申请号：US14607572
申请日：2015-01-28
CPC分类号： H05K3/007 , H05K1/0271 , H05K3/0026 , H05K3/188 , H05K3/28 , H05K3/4038 , H05K3/4682 , H05K2203/0152 , H05K2203/016 , H05K2203/1377
摘要： The present invention provides a substrate structure and a method of fabricating the substrate substrure. The method includes: forming a first wiring layer on a first carrier, forming a dielectric layer on the first wiring layer, forming a second wiring layer on the dielectric layer, forming an insulating protection layer on the second wiring layer, forming a second carrier on the insulative protection layer, and remvoing the first carrier. The formation of the second carrier provides the substrate structure with adequate rigidity to avoid breakage or warpage such that the miniaturization requirement can be satisfied.
摘要翻译： 本发明提供一种衬底结构和制造衬底基底的方法。 该方法包括：在第一载体上形成第一布线层，在第一布线层上形成电介质层，在介电层上形成第二布线层，在第二布线层上形成绝缘保护层，在第二布线层上形成第二载体 绝缘保护层，并提供第一个载体。 第二载体的形成为基板结构提供足够的刚度以避免断裂或翘曲，从而可以满足小型化要求。
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公开(公告)号：US20160079170A1
公开(公告)日：2016-03-17
申请号：US14708249
申请日：2015-05-10
发明人： Yu-Cheng Pai , Wei-Chung Hsiao , Shih-Chao Chiu , Chun-Hsien Lin , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
IPC分类号： H01L23/538 , H01L21/56 , H01L21/48 , H01L25/00 , H01L23/00 , H01L25/065
CPC分类号： H01L23/5389 , H01L21/568 , H01L23/3128 , H01L24/19 , H01L24/96 , H01L2224/04105 , H01L2224/16227 , H01L2224/97 , H01L2924/15311 , H01L2224/81
摘要： A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.
摘要翻译： 提供半导体封装结构及其制造方法。 半导体封装结构包括具有相对的第一和第二表面的封装体; 多个第一导电焊盘和形成在封装主体的第一表面上的多个第二导电焊盘; 嵌入在所述封装主体中并电连接到所述第一导电焊盘的半导体部件; 以及嵌入在所述封装主体中的多个导电元件，每个所述导电元件具有电连接到所述第二导电焊盘中的相应一个的第一端和与所述第一端相对并从所述封装体的所述第二表面露出的第二端 。 由于半导体部件嵌入封装主体中，所以半导体封装结构的厚度减小。
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公开(公告)号：US10141266B2
公开(公告)日：2018-11-27
申请号：US15621337
申请日：2017-06-13
发明人： Yu-Cheng Pai , Wei-Chung Hsiao , Shih-Chao Chiu , Chun-Hsien Lin , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
IPC分类号： H01L23/48 , H01L23/538 , H01L23/00 , H01L21/56 , H01L23/31
摘要： A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.
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公开(公告)号：US10068842B2
公开(公告)日：2018-09-04
申请号：US15648089
申请日：2017-07-12
发明人： Shih-Chao Chiu , Chun-Hsien Lin , Yu-Cheng Pai , Wei-Chung Hsiao , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
IPC分类号： H01L23/498 , H01L21/48 , H01L23/31
摘要： A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.
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公开(公告)号：US20170294372A1
公开(公告)日：2017-10-12
申请号：US15632669
申请日：2017-06-26
发明人： Chia-Cheng Chen , Chi-Ching Ho , Shao-Tzu Tang , Yu-Che Liu , Ying-Chou Tsai
IPC分类号： H01L23/498 , H01L23/00 , H01L23/31 , H01L21/48 , H01L21/56
CPC分类号： H01L23/49838 , H01L21/4853 , H01L21/56 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/3128 , H01L23/49816 , H01L23/49894 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/85 , H01L2221/68345 , H01L2224/05554 , H01L2224/16227 , H01L2224/16238 , H01L2224/2929 , H01L2224/29339 , H01L2224/32225 , H01L2224/45144 , H01L2224/48159 , H01L2224/48227 , H01L2224/48247 , H01L2224/49173 , H01L2224/73204 , H01L2224/73265 , H01L2224/81005 , H01L2224/81193 , H01L2224/81424 , H01L2224/81447 , H01L2224/83005 , H01L2224/85005 , H01L2924/00014 , H01L2924/10162 , H01L2924/181 , H01L2924/35121 , H01L2224/13099 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.
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公开(公告)号：US20170047240A1
公开(公告)日：2017-02-16
申请号：US15334569
申请日：2016-10-26
发明人： Yu-Cheng Pai , Chun-Hsien Lin , Shih-Chao Chiu , Wei-Chung Hsiao , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
IPC分类号： H01L21/683 , H01L23/498 , H01L21/48
CPC分类号： H01L21/6835 , H01L21/4857 , H01L21/486 , H01L23/498 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/17 , H01L2221/68345 , H01L2221/68359 , H01L2221/68381 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H05K3/20 , H05K3/4007 , H05K3/4682 , H05K2201/0367 , H05K2201/09563 , H05K2201/10674
摘要： A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.
摘要翻译： 提供了一种无芯封装基板，其包括：具有相对的第一和第二表面的电介质层; 所述第一电路层嵌入在所述电介质层中并且从所述电介质层的所述第一表面露出，其中所述第一电路层具有多个第一导电焊盘; 分别形成在第一导电焊盘上的多个突起元件，其中每个突出元件具有被外部导电元件封装的接触表面; 形成在电介质层的第二表面上的第二电路层; 以及形成在电介质层中的多个导电通孔，用于电连接第一电路层和第二电路层。 本发明由于突出元件和导电元件之间的大的接触面积而增强了第一导电焊盘和导电元件之间的接合。
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