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公开(公告)号：US20190259723A1
公开(公告)日：2019-08-22
申请号：US16403877
申请日：2019-05-06
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Yi-Cheih Chen , Sung-Huan Sun , Cheng-An Chang , Chien-Hung Wu , Fu-Tang Huang
IPC: H01L23/00
Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
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公开(公告)号：US20170309585A1
公开(公告)日：2017-10-26
申请号：US15645560
申请日：2017-07-10
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Yi-Cheih Chen , Sung-Huan Sun , Cheng-An Chang , Chien-Hung Wu , Fu-Tang Huang
IPC: H01L23/00
CPC classification number: H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/02166 , H01L2224/0231 , H01L2224/03019 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/03916 , H01L2224/0401 , H01L2224/05024 , H01L2224/05166 , H01L2224/05647 , H01L2224/10126 , H01L2224/11462 , H01L2224/1147 , H01L2224/11474 , H01L2224/1148 , H01L2224/11849 , H01L2224/119 , H01L2224/11916 , H01L2224/13007 , H01L2224/13024 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2924/014 , H01L2924/00014
Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
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公开(公告)号：US09735124B2
公开(公告)日：2017-08-15
申请号：US14957027
申请日：2015-12-02
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Yi-Cheih Chen , Sung-Huan Sun , Cheng-An Chang , Chien-Hung Wu , Fu-Tang Huang
CPC classification number: H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/02166 , H01L2224/0231 , H01L2224/03019 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/03916 , H01L2224/0401 , H01L2224/05024 , H01L2224/05166 , H01L2224/05647 , H01L2224/10126 , H01L2224/11462 , H01L2224/1147 , H01L2224/11474 , H01L2224/1148 , H01L2224/11849 , H01L2224/119 , H01L2224/11916 , H01L2224/13007 , H01L2224/13024 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2924/014 , H01L2924/00014
Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
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公开(公告)号：US09515007B2
公开(公告)日：2016-12-06
申请号：US14879254
申请日：2015-10-09
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Cheng-An Chang , Sung-Huan Sun , Chien-Hung Wu , Yi-Cheih Chen , Wen-Kai Liao
IPC: H01L23/48 , H01L23/498 , H01L23/00 , H01L23/31 , H01L23/528
CPC classification number: H01L23/481 , H01L23/3157 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/528 , H01L23/562 , H01L23/585 , H01L24/06 , H01L2224/0401 , H01L2924/10253 , H01L2924/3511
Abstract: A substrate structure includes: a substrate body defined with a layout area, a sealing member and a cutting area, the sealing member being adjacent to the layout area, and the cutting area being adjacent to the sealing member; a wiring layer formed on the layout area; an insulating layer formed on the layout area and the wiring layer; and a metal layer formed on the insulating layer and the layout area. The insulating layer is prevented from being delaminated due to the formation of the metal layer.
Abstract translation: 基板结构包括：限定有布局区域的基板主体，密封构件和切割区域，所述密封构件邻近所述布局区域，并且所述切割区域与所述密封构件相邻; 形成在布局区域上的布线层; 形成在布局区域和布线层上的绝缘层; 以及形成在绝缘层和布局区域上的金属层。 由于金属层的形成，绝缘层被防止分层。
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公开(公告)号：US20160190039A1
公开(公告)日：2016-06-30
申请号：US14879254
申请日：2015-10-09
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Cheng-An Chang , Sung-Huan Sun , Chien-Hung Wu , Yi-Cheih Chen , Wen-Kai Liao
IPC: H01L23/48 , H01L23/528 , H01L23/31 , H01L23/498 , H01L23/00
CPC classification number: H01L23/481 , H01L23/3157 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/528 , H01L23/562 , H01L23/585 , H01L24/06 , H01L2224/0401 , H01L2924/10253 , H01L2924/3511
Abstract: A substrate structure includes: a substrate body defined with a layout area, a sealing member and a cutting area, the sealing member being adjacent to the layout area, and the cutting area being adjacent to the sealing member; a wiring layer formed on the layout area; an insulating layer formed on the layout area and the wiring layer; and a metal layer formed on the insulating layer and the layout area. The insulating layer is prevented from being delaminated due to the formation of the metal layer.
Abstract translation: 基板结构包括：限定有布局区域的基板主体，密封构件和切割区域，密封构件邻近布置区域，并且切割区域与密封构件相邻; 形成在布局区域上的布线层; 形成在布局区域和布线层上的绝缘层; 以及形成在绝缘层和布局区域上的金属层。 由于金属层的形成，绝缘层被防止分层。
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Patent Agency Ranking
公开(公告)号：US20160079148A1
公开(公告)日：2016-03-17
申请号：US14667795
申请日：2015-03-25
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Cheng-An Chang , Sung-Huan Sun , Chien-Hung Wu , Yi-Cheih Chen , Wen-Kai Liao
IPC: H01L23/498 , H01L21/48
CPC classification number: H05K1/0298 , H01L23/3192 , H01L23/5226 , H01L23/525 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02125 , H01L2224/02311 , H01L2224/02313 , H01L2224/0235 , H01L2224/0236 , H01L2224/0239 , H01L2224/024 , H01L2224/0401 , H01L2224/05008 , H01L2224/05147 , H01L2224/05548 , H01L2224/05558 , H01L2224/05569 , H01L2224/05647 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2924/351 , H01L2924/3511 , H05K3/46 , H01L2924/00012 , H01L2924/014 , H01L2924/01047 , H01L2924/00014
Abstract: A substrate structure is provided, including: a carrier having at least a wiring area defined and positioned on a portion of a surface of the carrier; a first insulating layer formed on the wiring area; a wiring layer formed on the first insulating layer formed on the wiring area; and a second insulating layer formed on the wiring area. Therefore, a contact surface between the carrier and the first and second insulating layers is reduced by reducing the areas of the first and second insulating layers, whereby a substrate warpage due to mismatch of coefficients of thermal expansion (CTE) is avoided. The present invention further provides a method of manufacturing the substrate structure as described above.
Abstract translation: 提供了一种基板结构，包括：至少布线区域被定义并位于载体的表面的一部分上的载体; 形成在所述布线区域上的第一绝缘层; 形成在布线区域上形成的第一绝缘层上的布线层; 以及形成在布线区域上的第二绝缘层。 因此，通过减少第一绝缘层和第二绝缘层的面积来减小载体与第一绝缘层和第二绝缘层之间的接触表面，从而避免了由于热膨胀系数（CTE）失配引起的基板翘曲。 本发明还提供如上所述的制造衬底结构的方法。
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公开(公告)号：US09877386B2
公开(公告)日：2018-01-23
申请号：US14667795
申请日：2015-03-25
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Cheng-An Chang , Sung-Huan Sun , Chien-Hung Wu , Yi-Cheih Chen , Wen-Kai Liao
IPC: H05K1/02 , H05K3/46 , H01L23/522 , H01L23/525 , H01L23/00
CPC classification number: H05K1/0298 , H01L23/3192 , H01L23/5226 , H01L23/525 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02125 , H01L2224/02311 , H01L2224/02313 , H01L2224/0235 , H01L2224/0236 , H01L2224/0239 , H01L2224/024 , H01L2224/0401 , H01L2224/05008 , H01L2224/05147 , H01L2224/05548 , H01L2224/05558 , H01L2224/05569 , H01L2224/05647 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2924/351 , H01L2924/3511 , H05K3/46 , H01L2924/00012 , H01L2924/014 , H01L2924/01047 , H01L2924/00014
Abstract: A substrate structure is provided, including: a carrier having at least a wiring area defined and positioned on a portion of a surface of the carrier; a first insulating layer formed on the wiring area; a wiring layer formed on the first insulating layer formed on the wiring area; and a second insulating layer formed on the wiring area. Therefore, a contact surface between the carrier and the first and second insulating layers is reduced by reducing the areas of the first and second insulating layers, whereby a substrate warpage due to mismatch of coefficients of thermal expansion (CTE) is avoided. The present invention further provides a method of manufacturing the substrate structure as described above.
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公开(公告)号：US09398689B2
公开(公告)日：2016-07-19
申请号：US14463049
申请日：2014-08-19
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Cheng-An Chang , Sung-Huan Sun , Wen-Kai Liao , Chien-Hung Wu , Yi-Cheih Chen
IPC: H05K1/03 , H01L23/00 , H01L23/498 , H05K3/34 , H01L23/31
CPC classification number: H05K1/032 , H01L23/3192 , H01L23/49816 , H01L23/562 , H01L23/564 , H01L24/02 , H01L24/05 , H01L24/13 , H01L24/94 , H01L2224/02165 , H01L2224/02235 , H01L2224/02331 , H01L2224/0401 , H01L2224/05571 , H01L2224/10145 , H01L2224/13021 , H01L2224/13024 , H01L2224/131 , H01L2224/94 , H01L2924/351 , H01L2924/3512 , H01L2924/384 , H05K3/3452 , H05K3/3457 , H05K2201/09909 , H05K2203/041 , H01L2224/11 , H01L2924/014
Abstract: A substrate structure is provided, which includes: a substrate body having a plurality of conductive pads; an insulating layer formed on the substrate body and having a plurality of openings for correspondingly exposing the conductive pads; and a plurality of ring bodies formed in the openings and corresponding in position to edges of the conductive pads. As such, a plurality of conductive elements can be subsequently formed inside the ring bodies so as to be prevented by the ring bodies from expanding outward during a reflow process, thereby protecting the insulating layer from being compressed by the conductive elements and preventing cracking of the insulating layer.
Abstract translation: 提供了一种衬底结构，其包括：具有多个导电焊盘的衬底本体; 绝缘层，其形成在所述基板主体上并且具有用于相应地暴露所述导电焊盘的多个开口; 以及形成在所述开口中并且对应于所述导电垫的边缘的位置的多个环体。 因此，可以随后在环体内部形成多个导电元件，以便在回流过程中由环体向外扩张，从而保护绝缘层免受导电元件的压缩，并防止 绝缘层。
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公开(公告)号：US20150214168A1
公开(公告)日：2015-07-30
申请号：US14463049
申请日：2014-08-19
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Cheng-An Chang , Sung-Huan Sun , Wen-Kai Liao , Chien-Hung Wu , Yi-Cheih Chen
CPC classification number: H05K1/032 , H01L23/3192 , H01L23/49816 , H01L23/562 , H01L23/564 , H01L24/02 , H01L24/05 , H01L24/13 , H01L24/94 , H01L2224/02165 , H01L2224/02235 , H01L2224/02331 , H01L2224/0401 , H01L2224/05571 , H01L2224/10145 , H01L2224/13021 , H01L2224/13024 , H01L2224/131 , H01L2224/94 , H01L2924/351 , H01L2924/3512 , H01L2924/384 , H05K3/3452 , H05K3/3457 , H05K2201/09909 , H05K2203/041 , H01L2224/11 , H01L2924/014
Abstract: A substrate structure is provided, which includes: a substrate body having a plurality of conductive pads; an insulating layer formed on the substrate body and having a plurality of openings for correspondingly exposing the conductive pads; and a plurality of ring bodies formed in the openings and corresponding in position to edges of the conductive pads. As such, a plurality of conductive elements can be subsequently formed inside the ring bodies so as to be prevented by the ring bodies from expanding outward during a reflow process, thereby protecting the insulating layer from being compressed by the conductive elements and preventing cracking of the insulating layer.
Abstract translation: 提供了一种衬底结构，其包括：具有多个导电焊盘的衬底本体; 绝缘层，其形成在所述基板主体上并且具有用于相应地暴露所述导电焊盘的多个开口; 以及形成在所述开口中并且对应于所述导电垫的边缘的位置的多个环体。 因此，可以随后在环体内部形成多个导电元件，以便在回流过程中由环体向外扩张，从而保护绝缘层免受导电元件的压缩，并防止 绝缘层。
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公开(公告)号：US10325872B2
公开(公告)日：2019-06-18
申请号：US15645560
申请日：2017-07-10
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Yi-Cheih Chen , Sung-Huan Sun , Cheng-An Chang , Chien-Hung Wu , Fu-Tang Huang
Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
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