公开(公告)号：US07621041B2

公开(公告)日：2009-11-24

申请号：US11451763

申请日：2006-06-13

申请人： Sounak Banerji ,  G. Sidney Cox ,  Karl Hartmann Dietz

发明人： Sounak Banerji ,  G. Sidney Cox ,  Karl Hartmann Dietz

IPC分类号： H05K3/30

CPC分类号： H05K1/162 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49894 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K3/4602 ,  H05K3/4626 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2203/066 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49156 ,  Y10T29/49165

摘要： The present invention relates to methods of forming multilayer structures and the structures themselves. In one embodiment, a method of forming a multilayer structure comprises: providing a dielectric composition comprising paraelectric filler and polymer wherein the paraelectric filler has a dielectric constant between 50 and 150; applying the dielectric composition to a carrier film thus forming a multilayer film comprising a dielectric layer and carrier film layer; laminating the multilayer film to a circuitized core wherein the dielectric layer of the multilayer film is facing the circuitized core; and removing the carrier film layer from the dielectric layer prior to processing; applying a metallic layer to the dielectric layer wherein the circuitized core, dielectric layer and metallic layer form a planar capacitor; and processing the planar capacitor to form a multilayer structure.

摘要翻译： 本发明涉及形成多层结构和结构本身的方法。 在一个实施方案中，形成多层结构的方法包括：提供包含顺电填料和聚合物的电介质组合物，其中所述顺电填料具有介于50和150之间的介电常数; 将电介质组合物施加到载体膜上，从而形成包括电介质层和载体膜层的多层膜; 将多层膜层叠到电路化芯，其中多层膜的电介质层面向电路化芯; 在处理之前从所述介电层除去所述载体膜层; 将金属层施加到所述电介质层，其中所述电路化芯，电介质层和金属层形成平面电容器; 并处理该平面电容器以形成多层结构。

公开(公告)号：US07613007B2

公开(公告)日：2009-11-03

申请号：US11289994

申请日：2005-11-30

申请人： Daniel Irwin Amey, Jr. ,  Sounak Banerji ,  William J. Borland ,  Karl Hartmann Dietz ,  David Ross McGregor ,  Attiganal N. Sreeram

发明人： Daniel Irwin Amey, Jr. ,  Sounak Banerji ,  William J. Borland ,  Karl Hartmann Dietz ,  David Ross McGregor ,  Attiganal N. Sreeram

IPC分类号： H05K1/18

CPC分类号： H01L23/66 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09763 ,  H01L2224/0401

摘要： The present invention relates to a device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor; and at least one planar capacitor laminate; wherein said planar capacitor laminate serves as a low inductance path to supply a charge to said at least one embedded singulated capacitor; and wherein said at least one embedded singulated capacitor is connected in parallel to at least one of the said planar capacitor laminates; and wherein said power core is interconnected to at least one signal layer.

摘要翻译： 本发明涉及一种包括功率核心的器件，其中所述功率核心包括：至少一个嵌入的单个电容器层，其包含至少一个嵌入式单电容器; 和至少一个平面电容器层压体; 其中所述平面电容器层叠体用作低电感路径以向所述至少一个嵌入式分离电容器提供电荷; 并且其中所述至少一个嵌入式单电容器与所述平面电容器层压体中的至少一个并联连接; 并且其中所述功率核心与至少一个信号层相互连接。

公开(公告)号：US07778038B2

公开(公告)日：2010-08-17

申请号：US11289961

申请日：2005-11-30

申请人： David Ross McGregor ,  Daniel Irwin Amey, Jr. ,  Sounak Banerji ,  William J. Borland ,  Karl Hartmann Dietz ,  Attiganal N. Sreeram

发明人： David Ross McGregor ,  Daniel Irwin Amey, Jr. ,  Sounak Banerji ,  William J. Borland ,  Karl Hartmann Dietz ,  Attiganal N. Sreeram

IPC分类号： H05K1/18

CPC分类号： H05K1/186 ,  H05K1/0231 ,  H05K1/162 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/10636 ,  Y02P70/611

摘要： The present invention relates to a power core comprising: at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor; and at least one planar capacitor laminate; wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor; and wherein said embedded SMT discrete chip capacitor is connected in parallel to said planar capacitor laminate.

摘要翻译： 电源核心技术领域本发明涉及一种功率核心，包括：至少一个嵌入式表面贴装技术（SMT）离散芯片电容器层，包括至少一个嵌入式SMT分立片式电容器; 和至少一个平面电容器层压板; 其中至少一个平面电容器层叠体用作低电感路径以向至少一个嵌入式SMT分立片式电容器提供电荷; 并且其中所述嵌入式SMT分立片式电容器与所述平面电容层叠体并联连接。

公开(公告)号：US20060133057A1

公开(公告)日：2006-06-22

申请号：US11289961

申请日：2005-11-30

申请人： David McGregor ,  Daniel Amey ,  Sounak Banerji ,  William Borland ,  Karl Dietz ,  Attiganal Sreeram

发明人： David McGregor ,  Daniel Amey ,  Sounak Banerji ,  William Borland ,  Karl Dietz ,  Attiganal Sreeram

IPC分类号： H05K7/06

CPC分类号： H05K1/186 ,  H05K1/0231 ,  H05K1/162 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/10636 ,  Y02P70/611

摘要： The present invention relates to a power core comprising: at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor; and at least one planar capacitor laminate; wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor; and wherein said embedded SMT discrete chip capacitor is connected in parallel to said planar capacitor laminate.

摘要翻译： 电源核心技术领域本发明涉及一种功率核心，包括：至少一个嵌入式表面贴装技术（SMT）离散芯片电容器层，包括至少一个嵌入式SMT分立片式电容器; 和至少一个平面电容器层压板; 其中至少一个平面电容器层叠体用作低电感路径以向至少一个嵌入式SMT分立片式电容器提供电荷; 并且其中所述嵌入式SMT分立片式电容器与所述平面电容层叠体并联连接。

公开(公告)号：US20060158828A1

公开(公告)日：2006-07-20

申请号：US11289884

申请日：2005-11-30

申请人： Daniel Amey ,  Sounak Banerji ,  William Borland ,  David McGregor ,  Attiganal Sreeram ,  Karl Dietz

发明人： Daniel Amey ,  Sounak Banerji ,  William Borland ,  David McGregor ,  Attiganal Sreeram ,  Karl Dietz

IPC分类号： H01G4/06

CPC分类号： H05K1/162 ,  H01L2924/0002 ,  H05K3/4641 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09763 ,  H01L2924/00

摘要： A power core comprising: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor; and at least one planar capacitor laminate; wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded singulated capacitor; and wherein said embedded singulated capacitor is connected in parallel to said planar capacitor laminate.

摘要翻译： 一种功率核心，包括：至少一个嵌入的单个电容器层，其包含至少一个嵌入式单电容器; 和至少一个平面电容器层压板; 其中至少一个平面电容器层叠体用作低电感路径，以向至少一个嵌入的单个电容器提供电荷; 并且其中所述嵌入式单电容器与所述平面电容器层压体并联连接。

公开(公告)号：US20070006435A1

公开(公告)日：2007-01-11

申请号：US11451763

申请日：2006-06-13

申请人： Sounak Banerji ,  G. Cox ,  Karl Dietz

发明人： Sounak Banerji ,  G. Cox ,  Karl Dietz

IPC分类号： H01G7/00 ,  H01G4/06

CPC分类号： H05K1/162 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49894 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K3/4602 ,  H05K3/4626 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2203/066 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49156 ,  Y10T29/49165

摘要： The present invention relates to methods of forming multilayer structures and the structures themselves. In one embodiment, a method of forming a multilayer structure comprising: providing a dielectric composition comprising: paraelectric filler and polymer wherein said paraelectric filler has a dielectric constant between 50 and 150; applying said dielectric composition to a carrier film thus forming a multilayer film comprising a dielectric layer and carrier film layer; laminating said multilayer film to a circuitized core wherein the dielectric layer of said multilayer film is facing said circuitized core; and removing said carrier film layer from said dielectric layer prior to processing; applying a metallic layer to said dielectric layer wherein said circuitized core, dielectric layer and metallic layer form a planar capacitor; and processing said planar capacitor to form a multilayer structure.

摘要翻译： 本发明涉及形成多层结构和结构本身的方法。 在一个实施方案中，形成多层结构的方法包括：提供电介质组合物，其包括：顺电填料和聚合物，其中所述顺电填料具有介于50和150之间的介电常数; 将所述电介质组合物施加到载体膜上，从而形成包含介电层和载体膜层的多层膜; 将所述多层膜层压到电路化芯，其中所述多层膜的电介质层面向所述电路化芯; 以及在处理之前从所述电介质层去除所述载体膜层; 将金属层施加到所述电介质层，其中所述电路化芯，电介质层和金属层形成平面电容器; 并处理所述平面电容器以形成多层结构。

公开(公告)号：US20060138591A1

公开(公告)日：2006-06-29

申请号：US11289994

申请日：2005-11-30

申请人： Daniel Amey ,  Sounak Banerji ,  William Borland ,  Karl Dietz ,  David McGregor ,  Attiganal Sreeram

发明人： Daniel Amey ,  Sounak Banerji ,  William Borland ,  Karl Dietz ,  David McGregor ,  Attiganal Sreeram

IPC分类号： H01L29/00

CPC分类号： H01L23/66 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09763 ,  H01L2224/0401

摘要： The present invention relates to a device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor; and at least one planar capacitor laminate; wherein said planar capacitor laminate serves as a low inductance path to supply a charge to said at least one embedded singulated capacitor; and wherein said at least one embedded singulated capacitor is connected in parallel to at least one of the said planar capacitor laminates; and wherein said power core is interconnected to at least one signal layer.

摘要翻译： 本发明涉及一种包括功率核心的器件，其中所述功率核心包括：至少一个嵌入的单个电容器层，其包含至少一个嵌入式单电容器; 和至少一个平面电容器层压板; 其中所述平面电容器层叠体用作低电感路径以向所述至少一个嵌入式分离电容器提供电荷; 并且其中所述至少一个嵌入式单电容器与所述平面电容器层压体中的至少一个并联连接; 并且其中所述功率核心与至少一个信号层相互连接。

公开(公告)号：US07285321B2

公开(公告)日：2007-10-23

申请号：US10706000

申请日：2003-11-12

申请人： Kuppsuamy Kanakarajan ,  Brian C. Auman ,  Sounak Banerji

发明人： Kuppsuamy Kanakarajan ,  Brian C. Auman ,  Sounak Banerji

IPC分类号： B32B3/00 ,  H05K1/00

CPC分类号： B32B27/281 ,  B32B7/02 ,  B32B15/08 ,  B32B27/08 ,  B32B27/34 ,  B32B2250/40 ,  C08G73/1042 ,  C08G73/1082 ,  C09J179/08 ,  H01L2924/0002 ,  H05K1/0346 ,  H05K1/036 ,  H05K3/4626 ,  H05K2201/0154 ,  H05K2201/0195 ,  Y10T428/24917 ,  Y10T428/31721 ,  H01L2924/00

摘要： The present invention relates to a multi-layer laminate having a low glass transition temperature polyimide layer, a high glass transition temperature polyimide layer, and a conductive layer.The low glass transition temperature polyimide layer is synthesized by contacting an aromatic dianhydride with a diamine component, the diamine component comprising about 50 to about 90 mole % aliphatic diamine (the remainder being aromatic diamine) having the structural formula H2N—R—NH2 wherein R is hydrocarbon from C4 to C16. The low glass transition polyimide is an adhesive and has a glass transition temperature in the range of from 150° C. to 200° C.The high glass transition temperature polyimide layer has a glass transition temperature above the low glass transition temperature polyimide layer and is a thermoset polyimide.A multi-layer-layer substrate of the present invention has the high glass transition temperature polyimide layer positioned between the conductive layer and the low glass transition polyimide, or optionally contains an additional low glass transition temperature polyimide positioned between the conductive layer and the high glass transition polyimide layer.

摘要翻译： 本发明涉及具有低玻璃化转变温度聚酰亚胺层，高玻璃化转变温度聚酰亚胺层和导电层的多层层压体。 通过使芳族二酐与二胺组分接触来合成低玻璃化转变温度聚酰亚胺层，二胺组分包含具有结构式H 2 2的约50至约90摩尔％的脂族二胺（余量为芳族二胺） 其中R是C 4〜C 16的烃。 低玻璃化转变聚酰亚胺是粘合剂并且玻璃化转变温度在150℃至200℃的范围内。高玻璃化转变温度聚酰亚胺层的玻璃化转变温度高于低玻璃化转变温度聚酰亚胺层，并且是 热固性聚酰亚胺。 本发明的多层基板具有位于导电层和低玻璃化转变聚酰亚胺之间的高玻璃化转变温度聚酰亚胺层，或任选地包含位于导电层和高玻璃之间的额外的低玻璃化转变温度聚酰亚胺 过渡聚酰亚胺层。

公开(公告)号：US20050100719A1

公开(公告)日：2005-05-12

申请号：US10706000

申请日：2003-11-12

申请人： Kuppsuamy Kanakarajan ,  Brian Auman ,  Sounak Banerji

发明人： Kuppsuamy Kanakarajan ,  Brian Auman ,  Sounak Banerji

IPC分类号： B32B15/08 ,  B32B27/34 ,  C08G73/10 ,  C09D179/08 ,  C09J179/08 ,  H01L23/14 ,  H05K1/00 ,  H05K1/03 ,  H05K3/38 ,  H05K3/46 ,  B32B7/00

CPC分类号： B32B27/281 ,  B32B7/02 ,  B32B15/08 ,  B32B27/08 ,  B32B27/34 ,  B32B2250/40 ,  C08G73/1042 ,  C08G73/1082 ,  C09J179/08 ,  H01L2924/0002 ,  H05K1/0346 ,  H05K1/036 ,  H05K3/4626 ,  H05K2201/0154 ,  H05K2201/0195 ,  Y10T428/24917 ,  Y10T428/31721 ,  H01L2924/00

摘要： The present invention relates to a multi-layer laminate having a low glass transition temperature polyimide layer, a high glass transition temperature polyimide layer, and a conductive layer. The low glass transition temperature polyimide layer is synthesized by contacting an aromatic dianhydride with a diamine component, the diamine component comprising about 50 to about 90 mole % aliphatic diamine (the remainder being aromatic diamine) having the structural formula H2N—R—NH2 wherein R is hydrocarbon from C4 to C16. The low glass transition polyimide is an adhesive and has a glass transition temperature in the range of from 150° C. to 200° C. The high glass transition temperature polyimide layer has a glass transition temperature above the low glass transition temperature polyimide layer and is a thermoset polyimide. A multi-layer-layer substrate of the present invention has the high glass transition temperature polyimide layer positioned between the conductive layer and the low glass transition polyimide, or optionally contains an additional low glass transition temperature polyimide positioned between the conductive layer and the high glass transition polyimide layer.

摘要翻译： 本发明涉及具有低玻璃化转变温度聚酰亚胺层，高玻璃化转变温度聚酰亚胺层和导电层的多层层压体。 通过使芳族二酐与二胺组分接触来合成低玻璃化转变温度聚酰亚胺层，二胺组分包含具有结构式H 2 2的约50至约90摩尔％的脂族二胺（余量为芳族二胺） 其中R是C 4〜C 16的烃。 低玻璃化转变聚酰亚胺是粘合剂并且玻璃化转变温度在150℃至200℃的范围内。高玻璃化转变温度聚酰亚胺层的玻璃化转变温度高于低玻璃化转变温度聚酰亚胺层，并且是 热固性聚酰亚胺。 本发明的多层基板具有位于导电层和低玻璃化转变聚酰亚胺之间的高玻璃化转变温度聚酰亚胺层，或任选地包含位于导电层和高玻璃之间的额外的低玻璃化转变温度聚酰亚胺 过渡聚酰亚胺层。