公开(公告)号：US08969920B2

公开(公告)日：2015-03-03

申请号：US13824248

申请日：2011-07-06

申请人： Makoto Kiyama ,  Yu Saitoh ,  Masaya Okada ,  Masaki Ueno ,  Seiji Yaegashi ,  Kazutaka Inoue ,  Mitsunori Yokoyama

发明人： Makoto Kiyama ,  Yu Saitoh ,  Masaya Okada ,  Masaki Ueno ,  Seiji Yaegashi ,  Kazutaka Inoue ,  Mitsunori Yokoyama

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/423

CPC分类号： H01L29/778 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/7789

摘要： A vertical semiconductor device in which pinch-off characteristics and breakdown voltage characteristics can be stably improved by fixing the electric potential of a p-type GaN barrier layer with certainty is provided. The semiconductor device includes a GaN-based stacked layer having an opening, a regrown layer including a channel located so as to cover a wall surface of the opening, an n+-type source layer that is in ohmic contact with the source electrode, a p-type GaN barrier layer, and a p+-type GaN-based supplementary layer located between the p-type GaN barrier layer and the n+-type source layer. The p+-type GaN-based supplementary layer and the n+-type source layer form a tunnel junction to fix the electric potential of the p-type GaN barrier layer at a source potential.

摘要翻译： 提供了通过确定地固定p型GaN势垒层的电位可以稳定地提高夹断特性和击穿电压特性的垂直半导体器件。 半导体器件包括具有开口的GaN基层叠层，包含覆盖开口壁面的沟道的再生长层，与源电极欧姆接触的n +型源极，p 位于p型GaN势垒层和n +型源极层之间的p +型GaN基辅助层。 p +型GaN基辅助层和n +型源极层形成隧道结，以将p型GaN阻挡层的电位固定在源极电位。

公开(公告)号：US20140203329A1

公开(公告)日：2014-07-24

申请号：US14123738

申请日：2011-06-03

申请人： Yu Saitoh ,  Masaya Okada ,  Yusuke Yoshizumi ,  Makoto Kiyama ,  Masaki Ueno ,  Koji Katayama ,  Takao Nakamura

发明人： Yu Saitoh ,  Masaya Okada ,  Yusuke Yoshizumi ,  Makoto Kiyama ,  Masaki Ueno ,  Koji Katayama ,  Takao Nakamura

IPC分类号： H01L29/66 ,  H01L29/778

CPC分类号： H01L29/66462 ,  H01L21/02389 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/30621 ,  H01L21/3085 ,  H01L21/3086 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/7788 ,  H01L29/7789

摘要： Provided is a nitride electronic device having a structure that allows the reduction of leakage by preventing the carrier concentration from increasing in a channel layer. An inclined surface and a primary surface of a semiconductor stack extend along first and second reference planes R1, R2, respectively. The primary surface of the stack is inclined at an angle ranging from 5 to 40 degrees with respect to a reference axis indicating a c-axis direction of hexagonal group III nitride. An axis normal to the plane R1 and the axis form an angle smaller than the angle an axis normal to the plane R2 and the axis form. The oxygen concentration of the channel layer is lower than 1×1017 cm−3. It becomes possible to avoid increase in carrier concentration of the channel layer caused by the oxygen addition, thereby reducing leakage current via the channel layer in the transistor.

摘要翻译： 本发明提供一种氮化物电子器件，其具有通过防止载流子浓度在沟道层中增加而允许减少泄漏的结构。 半导体堆叠的倾斜表面和主表面分别沿着第一和第二参考平面R1，R2延伸。 堆叠的主表面相对于表示六方晶III族氮化物的c轴方向的参考轴线以5至40度的角度倾斜。 与平面R1和轴垂直的轴线形成比垂直于平面R2的轴线和轴线的角度小的角度。 通道层的氧浓度低于1×1017cm-3。 可以避免由氧添加引起的沟道层的载流子浓度增加，从而减小晶体管中的沟道层的漏电流。

公开(公告)号：US20140110758A1

公开(公告)日：2014-04-24

申请号：US14124600

申请日：2011-06-08

申请人： Yu Saitoh ,  Masaya Okada ,  Masaki Ueno ,  Makoto Kiyama

发明人： Yu Saitoh ,  Masaya Okada ,  Masaki Ueno ,  Makoto Kiyama

IPC分类号： H01L29/778 ,  H01L29/66

CPC分类号： H01L29/66431 ,  H01L29/0623 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/8128

摘要： The semiconductor device is formed in the form of a GaN-based stacked layer including an n-type drift layer 4, a p-type layer 6, and an n-type top layer 8. The semiconductor device includes a regrown layer 27 formed so as to cover a portion of the GaN-based stacked layer that is exposed to an opening 28, the regrown layer 27 including a channel. The channel is two-dimensional electron gas formed at an interface between the electron drift layer and the electron supply layer. When the electron drift layer 22 is assumed to have a thickness of d, the p-type layer 6 has a thickness in the range of d to 10d, and a graded p-type impurity layer 7 whose concentration decreases from a p-type impurity concentration in the p-type layer is formed so as to extend from a (p-type layer/n-type top layer) interface to the inside of the n-type top layer.

摘要翻译： 半导体器件形成为包括n型漂移层4，p型层6和n型顶层8的GaN基叠层的形式。半导体器件包括如下形成的再生长层27 为了覆盖暴露于开口28的GaN基叠层的一部分，再生长层27包括沟道。 通道是在电子漂移层和电子供给层之间的界面处形成的二维电子气。 当假定电子漂移层22的厚度为d时，p型层6的厚度在d至10d的范围内，并且p型杂质层7的浓度从p型杂质降低 从（p型层/ n型顶层）界面向n型顶层的内部形成p型层的浓度。

公开(公告)号：US20130168739A1

公开(公告)日：2013-07-04

申请号：US13824248

申请日：2011-07-06

申请人： Makoto Kiyama ,  Yu Saitoh ,  Masaya Okada ,  Masaki Ueno ,  Seiji Yaegashi ,  Kazutaka Inoue ,  Mitsunori Yokoyama

发明人： Makoto Kiyama ,  Yu Saitoh ,  Masaya Okada ,  Masaki Ueno ,  Seiji Yaegashi ,  Kazutaka Inoue ,  Mitsunori Yokoyama

IPC分类号： H01L29/778 ,  H01L29/66

CPC分类号： H01L29/778 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/7789

摘要： A vertical semiconductor device in which pinch-off characteristics and breakdown voltage characteristics can be stably improved by fixing the electric potential of a p-type GaN barrier layer with certainty is provided. The semiconductor device includes a GaN-based stacked layer having an opening, a regrown layer including a channel located so as to cover a wall surface of the opening, an n+-type source layer that is in ohmic contact with the source electrode, a p-type GaN barrier layer, and a p+-type GaN-based supplementary layer located between the p-type GaN barrier layer and the n+-type source layer. The p+-type GaN-based supplementary layer and the n+-type source layer form a tunnel junction to fix the electric potential of the p-type GaN barrier layer at a source potential.

摘要翻译： 提供了通过确定地固定p型GaN势垒层的电位可以稳定地提高夹断特性和击穿电压特性的垂直半导体器件。 半导体器件包括具有开口的GaN基层叠层，包含覆盖开口壁面的沟道的再生长层，与源电极欧姆接触的n +型源极，p 位于p型GaN势垒层和n +型源极层之间的p +型GaN基辅助层。 p +型GaN基辅助层和n +型源极层形成隧道结，以将p型GaN阻挡层的电位固定在源极电位。

公开(公告)号：US08981428B2

公开(公告)日：2015-03-17

申请号：US13822591

申请日：2011-07-06

申请人： Yu Saitoh ,  Masaya Okada ,  Masaki Ueno ,  Makoto Kiyama

发明人： Yu Saitoh ,  Masaya Okada ,  Masaki Ueno ,  Makoto Kiyama

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L21/30 ,  H01L21/02 ,  H01L29/20 ,  H01L29/423

CPC分类号： H01L29/7788 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/3006 ,  H01L29/2003 ,  H01L29/4238 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7789

摘要： There are provided a semiconductor device in which a drain leak current can be reduced in the transistor operation while high vertical breakdown voltage is achieved and a method for producing the semiconductor device. In the semiconductor device, an opening 28 that extends from an n+-type contact layer 8 and reaches an n-type drift layer 4 through a p-type barrier layer 6 is formed. The semiconductor device includes a regrown layer 27 located so as to cover portions of the p-type barrier layer 6 and the like that are exposed to the opening, the regrown layer 27 including an undoped GaN channel layer 22 and a carrier supply layer 26; an insulating layer 9 located so as to cover the regrown layer 27; and a gate electrode G located on the insulating layer 9. In the p-type barrier layer, the Mg concentration A (cm−3)and the hydrogen concentration B (cm−3) satisfy 0.1

摘要翻译： 提供了一种半导体器件，其中在实现高的垂直击穿电压的同时，在晶体管操作中可以减小漏极漏电流，以及制造半导体器件的方法。 在半导体器件中，形成从n +型接触层8延伸并通过p型阻挡层6到达n型漂移层4的开口28。 半导体器件包括再生长层27，其被覆盖以覆盖暴露于开口的p型阻挡层6等的部分，再生长层27包括未掺杂的GaN沟道层22和载流子供给层26; 定位成覆盖再生长层27的绝缘层9; 和位于绝缘层9上的栅电极G.在p型阻挡层中，Mg浓度A（cm-3）和氢浓度B（cm-3）满足0.1