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    Method of driving ferroelectric gate transistor memory cell
    1.
    发明授权
    Method of driving ferroelectric gate transistor memory cell 失效
    驱动铁电栅晶体管存储单元的方法

    公开(公告)号：US5666305A

    公开(公告)日：1997-09-09

    申请号：US404300

    申请日：1995-03-14

    申请人： Takashi Mihara ,  Hiroshi Nakano ,  Hiroyuki Yoshimori ,  Shuzo Hiraide

    发明人： Takashi Mihara ,  Hiroshi Nakano ,  Hiroyuki Yoshimori ,  Shuzo Hiraide

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22

    摘要： A ferroelectric gate transistor has a structure in which n-type source and drain regions are formed on a p-type semiconductor, a ferroelectric thin film is formed on a channel region between the source and drain regions, and a gate electrode is formed thereon. Memory information is erased by applying a voltage V.sub.g to the ferroelectric to cause poling in the first direction. The memory information is written by applying a voltage V.sub.W lower than a coercive voltage of the ferroelectric and having a polarity opposite to that of the voltage V.sub.g to the ferroelectric. The memory information is read out by applying a voltage V.sub.DR lower than the voltage V.sub.W and having a polarity opposite to that of the voltage V.sub.g to the drain to read a drain current I.sub.DS.

    摘要翻译： 铁电栅极晶体管具有在p型半导体上形成n型源极和漏极区域的结构，在源极和漏极区域之间的沟道区域上形成铁电薄膜，并且在其上形成栅极电极。 通过向铁电体施加电压Vg以在第一方向上引起极化而擦除存储器信息。 通过施加低于铁电体的矫顽电压的电压VW并将其与电压Vg的极性相反的电压写入铁电体来写入存储器信息。 通过将低于电压VW的电压VDR施加到漏极以读出漏极电流IDS，读出存储器信息。

    Ferroelectric memory and non-volatile memory cell for same
    5.
    发明授权
    Ferroelectric memory and non-volatile memory cell for same 失效
    铁电存储器和非易失性存储器单元相同

    公开(公告)号：US5541870A

    公开(公告)日：1996-07-30

    申请号：US330989

    申请日：1994-10-28

    申请人： Takashi Mihara ,  Hitoshi Watanabe ,  Hiroyuki Yoshimori ,  Carlos A. Paz de Araujo ,  Larry D. McMillan

    发明人： Takashi Mihara ,  Hitoshi Watanabe ,  Hiroyuki Yoshimori ,  Carlos A. Paz de Araujo ,  Larry D. McMillan

    IPC分类号： G11C17/00 ,  G11C11/22 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11502 ,  G11C11/22

    摘要： A non-volatile integrated circuit memory in which the memory cell includes a first transistor gate overlying a first channel region, a ferroelectric material overlying a second channel region, and a second transistor gate overlying a third channel region. The channel regions are connected in series, and preferably are contiguous portions of a single semiconducting channel. The firm channel is connected to a plate voltage that is 20% to 50% of the coercive voltage of the ferroelectric material. A sense amplifier is connected to the third channel region via a bit line. The rise of the bit line after reading a logic "1" state of the cell is prevented from disturbing the ferroelectric material by shutting off the third channel before the sense amplifier rises.

    摘要翻译： 一种非易失性集成电路存储器，其中存储单元包括覆盖第一沟道区的第一晶体管栅极，覆盖第二沟道区的铁电材料和覆盖第三沟道区的第二晶体管栅极。 通道区域串联连接，优选地是单个半导体通道的连续部分。 固体通道连接到铁电体的矫顽电压的20％至50％的板电压。 读出放大器通过位线连接到第三通道区域。 读出逻辑“1”状态之后的位线的上升通过在读出放大器上升之前切断第三通道来防止铁电材料的干扰。

    Process for fabricating ferroelectric integrated circuit
    6.
    发明授权
    Process for fabricating ferroelectric integrated circuit 失效
    铁电集成电路制造工艺

    公开(公告)号：US5466629A

    公开(公告)日：1995-11-14

    申请号：US383575

    申请日：1995-02-03

    申请人： Takashi Mihara ,  Hiroyuki Yoshimori ,  Hitoshi Watanabe ,  Larry D. McMillan ,  Carlos P. De Araujo

    发明人： Takashi Mihara ,  Hiroyuki Yoshimori ,  Hitoshi Watanabe ,  Larry D. McMillan ,  Carlos P. De Araujo

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L28/60 ,  H01L28/55

    摘要： An oversize ferroelectric capacitor is located against the contact hole to the MOSFET source/drain in a DRAM. A barrier layer made of titanium nitride, titanium tungsten, tantalum, titanium, tungsten, molybdenum, chromium, indium tin oxide, tin dioxide, ruthenium oxide, silicon, silicide, or polycide lies between the ferroelectric layer and the source drain. The barrier layer may act as the bottom electrode of the ferroelectric capacitor, or a separate bottom electrode made of platinum may be used. In another embodiment in which the barrier layer forms the bottom electrode, an oxide layer less than 5 nm thick is located between the barrier layer and the ferroelectric layer and the barrier layer is made of silicon, silicide, or polycide. A thin silicide layer forms and ohmic contact between the barrier layer and the source/drain. The capacitor and the barrier layer are patterned in a single mask step. The ends of the capacitor are stepped or tapered. In another embodiment both the bottom and top electrode may be made of silicon, silicide, polycide or a conductive oxide, such as indium tin oxide, tin dioxide, or ruthenium oxide.

    摘要翻译： 超大型铁电电容器位于DRAM中的MOSFET源极/漏极的接触孔处。 在铁电层和源极漏极之间，由氮化钛，钛钨，钽，钛，钨，钼，铬，氧化铟锡，二氧化锡，氧化钌，硅，硅化物或多晶硅化物形成的阻挡层。 阻挡层可以用作铁电电容器的底部电极，或者可以使用由铂制成的单独的底部电极。 在其中阻挡层形成底部电极的另一个实施例中，小于5nm厚的氧化物层位于势垒层和铁电层之间，阻挡层由硅，硅化物或多硅化物制成。 薄的硅化物层在阻挡层和源极/漏极之间形成欧姆接触。 在单个掩模步骤中对电容器和阻挡层进行图案化。 电容器的端部是阶梯式或锥形的。 在另一个实施例中，底部和顶部电极可以由硅，硅化物，多晶硅或导电氧化物，例如氧化铟锡，二氧化锡或氧化钌制成。

    Ferroelectric non-volatile memory unit
    8.
    发明授权
    Ferroelectric non-volatile memory unit 失效
    铁电非易失性存储单元

    公开(公告)号：US5523964A

    公开(公告)日：1996-06-04

    申请号：US224241

    申请日：1994-04-07

    申请人： Larry D. McMillan ,  Takashi Mihara ,  Hiroyuki Yoshimori ,  John W. Gregory ,  Carlos A. Paz de Araujo

    发明人： Larry D. McMillan ,  Takashi Mihara ,  Hiroyuki Yoshimori ,  John W. Gregory ,  Carlos A. Paz de Araujo

    IPC分类号： G11C14/00 ,  G11C11/22 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C11/22 ,  G11C11/223

    摘要： An integrated circuit non-volatile, non-destructive read-out memory unit includes a ferroelectric capacitor having first and second electrodes, a capacitance Cf, and an area Af, and a transistor having a gate, a source and a drain forming a gate capacitor having an area Ag and a gate capacitance Cg, a gate overlap b, and a channel depth a, with the capacitor first electrode connected to the gate of the transistor. The ferroelectric material has a dielectric constant .epsilon.f and the gate insulator has a dielectric constant .epsilon.g. A source of a constant reference voltage is connectable to the first electrode. A bit line connects to the second electrode. In one embodiment the first electrode and gate are the same conductive member. In another embodiment the second electrode and the gate are the same conductive member and the first electrode is formed by extensions of the transistor source and drains underlying the gate, with the ferroelectric material between the source and drain extensions and the gate. The memory unit has the parametric relationships: Cf

    摘要翻译： 集成电路非易失性非破坏性读出存储单元包括具有第一和第二电极的铁电电容器，电容Cf和区域Af，以及具有形成栅极电容器的栅极，源极和漏极的晶体管 具有面积Ag和栅极电容Cg，栅极重叠b和沟道深度a，其中电容器第一电极连接到晶体管的栅极。 铁电材料具有介电常数εf，栅极绝缘体具有介电常数εg。 恒定参考电压的源可连接到第一电极。 位线连接到第二电极。 在一个实施例中，第一电极和栅极是相同的导电构件。 在另一个实施例中，第二电极和栅极是相同的导电构件，并且第一电极由晶体管源的延伸和栅极下方的漏极形成，铁电材料在源极和漏极延伸部分之间以及栅极之间。 存储器单元具有参数关系：Cf <5xCg，Af / = 2a和epsilon g> / = epsilon f / 8。