公开(公告)号：US09595602B2

公开(公告)日：2017-03-14

申请号：US14418610

申请日：2012-09-07

申请人： Takayuki Hashimoto ,  Mutsuhiro Mori ,  Masahiro Masunaga

发明人： Takayuki Hashimoto ,  Mutsuhiro Mori ,  Masahiro Masunaga

IPC分类号： H01L29/78 ,  H01L29/739 ,  H01L29/423 ,  H02M7/537 ,  H01L29/06 ,  H02M1/08 ,  H02M7/5387

CPC分类号： H02M1/088 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1079 ,  H01L29/41708 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7394 ,  H01L29/7396 ,  H01L29/7397 ,  H02M1/08 ,  H02M7/003 ,  H02M7/537 ,  H02M7/5387 ,  H02M2001/0054

摘要： The present invention provides a switching device (100) for power conversion in which a first gate electrode (6), a p-type channel layer (2) having an n-type emitter region (3), a second gate electrode (13), and a p-type floating layer (15) are repeatedly arranged in order on the surface side of an n-type semiconductor substrate (1). An interval a between the two gates (6, 13) that sandwich the p-type channel layer (2) is configured to be smaller than an interval b between the two gates (13, 6) that sandwich the p-type floating layer (15). The first gate electrode (6) and the second gate electrode (13) are both supplied with drive signals having a time difference in drive timing.

摘要翻译： 本发明提供一种用于功率转换的开关装置（100），其中具有n型发射极区（3）的第一栅电极（6），p型沟道层（2），第二栅电极（13） ，并且在n型半导体衬底（1）的表面侧依次重复布置p型浮动层（15）。 夹着p型沟道层（2）的两个栅极（6,13）之间的间隔a被配置为小于夹着p型浮动层的两个栅极（13,6）之间的间隔b 15）。 第一栅电极（6）和第二栅电极（13）都被提供有驱动定时具有时差的驱动信号。

公开(公告)号：US20140334212A1

公开(公告)日：2014-11-13

申请号：US14364959

申请日：2011-12-15

申请人： Takayuki Hashimoto ,  Mutsuhiro Mori

发明人： Takayuki Hashimoto ,  Mutsuhiro Mori

IPC分类号： H01L29/739 ,  H01L29/10 ,  H02M7/537 ,  H01L29/88

CPC分类号： H01L29/7397 ,  H01L27/0727 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/7395 ,  H01L29/861 ,  H01L29/88 ,  H02M7/537

摘要： A semiconductor device of this invention (an IGBT with a built-in diode) includes: an n−-type drift layer 1; a p-type channel region 2 that is arranged in contact with the surface side of this n−-type drift layer 1; a gate electrode 5 that is provided in a trench T provided so as to penetrate this p-type channel region 2 and reach to the n−-type drift layer 1 through a gate insulating film 3; an n-type source region 4 that is provided so as to contact the trench T on the surface side of the p-type channel region 2; a high-concentration n-type region 6 that is arranged in contact with the back side of the n−-type drift layer 1; and a high-concentration p-type region 7 that is arranged in contact with the back side of this high-concentration n-type region 6; in which a junction of the high-concentration n-type region 6 and the high-concentration p-type region 7 is a tunnel junction. According to this semiconductor device, it is possible to form the IGBT and the diode on a single chip. Moreover, it is possible to avoid problems of “snap back” and “current concentration.”

摘要翻译： 本发明的半导体器件（具有内置二极管的IGBT）包括：n型漂移层1; 与该n型漂移层1的表面侧接触的p型沟道区域2; 设置在沟槽T中以设置成穿过该p型沟道区域2并通过栅极绝缘膜3到达n型漂移层1的栅电极5; n型源极区域4，其设置成与p型沟道区域2的表面侧的沟槽T接触; 配置成与n型漂移层1的背面接触的高浓度n型区域6; 以及与该高浓度n型区域6的背面接触的高浓度p型区域7; 其中高浓度n型区域6和高浓度p型区域7的结是隧道结。 根据该半导体器件，可以在单个芯片上形成IGBT和二极管。 此外，可以避免“回弹”和“当前集中”的问题。

公开(公告)号：US09349847B2

公开(公告)日：2016-05-24

申请号：US14364959

申请日：2011-12-15

申请人： Takayuki Hashimoto ,  Mutsuhiro Mori

发明人： Takayuki Hashimoto ,  Mutsuhiro Mori

IPC分类号： H01L29/66 ,  H01L21/332 ,  H01L29/739 ,  H01L29/861 ,  H01L29/08 ,  H01L29/10 ,  H01L27/07 ,  H01L29/88 ,  H02M7/537

CPC分类号： H01L29/7397 ,  H01L27/0727 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/7395 ,  H01L29/861 ,  H01L29/88 ,  H02M7/537

摘要： A semiconductor device of this invention (an IGBT with a built-in diode) includes: an n−-type drift layer 1; a p-type channel region 2 that is arranged in contact with the surface side of this n−-type drift layer 1; a gate electrode 5 that is provided in a trench T provided so as to penetrate this p-type channel region 2 and reach to the n−-type drift layer 1 through a gate insulating film 3; an n-type source region 4 that is provided so as to contact the trench T on the surface side of the p-type channel region 2; a high-concentration n-type region 6 that is arranged in contact with the back side of the n−-type drift layer 1; and a high-concentration p-type region 7 that is arranged in contact with the back side of this high-concentration n-type region 6; in which a junction of the high-concentration n-type region 6 and the high-concentration p-type region 7 is a tunnel junction. According to this semiconductor device, it is possible to form the IGBT and the diode on a single chip. Moreover, it is possible to avoid problems of “snap back” and “current concentration.”

摘要翻译： 本发明的半导体器件（具有内置二极管的IGBT）包括：n型漂移层1; 与该n型漂移层1的表面侧接触的p型沟道区域2; 设置在沟槽T中以设置成穿过该p型沟道区域2并通过栅极绝缘膜3到达n型漂移层1的栅电极5; n型源极区域4，其设置成与p型沟道区域2的表面侧的沟槽T接触; 配置成与n型漂移层1的背面接触的高浓度n型区域6; 以及与该高浓度n型区域6的背面接触的高浓度p型区域7; 其中高浓度n型区域6和高浓度p型区域7的结是隧道结。 根据该半导体器件，可以在单个芯片上形成IGBT和二极管。 此外，可以避免“回弹”和“当前集中”的问题。

公开(公告)号：US08653588B2

公开(公告)日：2014-02-18

申请号：US13553431

申请日：2012-07-19

申请人： So Watanabe ,  Masaki Shiraishi ,  Hiroshi Suzuki ,  Mutsuhiro Mori

发明人： So Watanabe ,  Masaki Shiraishi ,  Hiroshi Suzuki ,  Mutsuhiro Mori

IPC分类号： H01L29/66

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/66348

摘要： A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type on the first semiconductor layer; trenches in the first semiconductor layer; a semiconductor protruding part on the first semiconductor layer; a third semiconductor layer on the semiconductor protruding part; a fourth semiconductor layer on the third semiconductor layer; a gate insulating layer disposed along the trench; a first interlayer insulating layer disposed along the trench; a first conductive layer facing to the fourth semiconductor layer; a second conductive layer on the first interlayer insulating layer; a second interlayer insulating layer covering the second conductive layer; a third conductive layer on the third semiconductor layer and fourth semiconductor layer; a contacting part connecting the third conductive layer and third semiconductor layer; and a fourth conductive layer formed on the second semiconductor layer.

摘要翻译： 半导体器件包括：第一导电类型的第一半导体层; 在第一半导体层上的第二导电类型的第二半导体层; 第一半导体层中的沟槽; 在所述第一半导体层上的半导体突出部; 半导体突出部分上的第三半导体层; 第三半导体层上的第四半导体层; 栅极绝缘层，沿着沟槽设置; 沿沟槽设置的第一层间绝缘层; 面向第四半导体层的第一导电层; 在第一层间绝缘层上的第二导电层; 覆盖所述第二导电层的第二层间绝缘层; 在第三半导体层和第四半导体层上的第三导电层; 连接第三导电层和第三半导体层的接触部分; 以及形成在所述第二半导体层上的第四导电层。

公开(公告)号：US08411454B2

公开(公告)日：2013-04-02

申请号：US13239615

申请日：2011-09-22

申请人： Katsunori Azuma ,  Masamitsu Inaba ,  Mutsuhiro Mori ,  Kenichiro Nakajima

发明人： Katsunori Azuma ,  Masamitsu Inaba ,  Mutsuhiro Mori ,  Kenichiro Nakajima

IPC分类号： H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC分类号： H01G4/38 ,  B60K1/02 ,  B60K6/28 ,  B60K6/48 ,  B60L3/003 ,  B60L11/005 ,  B60L11/123 ,  B60L11/14 ,  B60L15/007 ,  B60L2200/26 ,  B60L2240/525 ,  B60L2270/145 ,  B60W10/06 ,  B60W10/08 ,  B60W20/00 ,  H01G2/04 ,  H01G4/228 ,  H01G9/008 ,  H01G9/08 ,  H01G9/14 ,  H01G9/26 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2924/00011 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H02M7/003 ,  Y02T10/6217 ,  Y02T10/6221 ,  Y02T10/6286 ,  Y02T10/645 ,  Y02T10/7022 ,  Y02T10/7077 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01033

摘要： A capacitor module in which the structure of a connecting portion is highly resistant against vibration and has a low inductance. The capacitor module includes a plurality of capacitors and a laminate made up of a first wide conductor and a second wide conductor joined in a layered form with an insulation sheet interposed between the first and second wide conductors. The laminate comprises a first flat portion including the plurality of capacitors which are supported thereon and electrically connected thereto, a second flat portion continuously extending from the first flat portion while being bent, and connecting portions formed at ends of the first flat portion and the second flat portion and electrically connected to the exterior.

摘要翻译： 一种电容器模块，其中连接部分的结构具有高抗振动性和低电感性。 电容器模块包括多个电容器和由第一宽导体和第二宽导体组成的层叠体，第一宽导体和第二宽导体以分层形式连接，绝缘片置于第一和第二宽导体之间。 层叠体包括：第一平坦部，其包括被支撑在其上并电连接的多个电容器;第二平坦部，其在弯曲的同时从第一平坦部连续地延伸;以及连接部，形成在第一平坦部和第二平坦部的端部 平坦部分并且电连接到外部。

公开(公告)号：US07875509B2

公开(公告)日：2011-01-25

申请号：US12103921

申请日：2008-04-16

申请人： Junichi Sakano ,  Kenji Hara ,  Shinji Shirakawa ,  Taiga Arai ,  Mutsuhiro Mori

发明人： Junichi Sakano ,  Kenji Hara ,  Shinji Shirakawa ,  Taiga Arai ,  Mutsuhiro Mori

IPC分类号： H01L21/84

CPC分类号： H01L29/7394 ,  H01L29/0878 ,  H01L29/66325 ,  H01L29/66681 ,  H01L29/7824

摘要： In a manufacturing method of a SOI type high withstand voltage semiconductor device formed on a support substrate via an insulation film, a small-sized semiconductor device having small dispersion of withstand voltage is manufactured by introducing impurities into the whole surface of a p-type or n-type SOI substrate having an impurity concentration of 2E14 cm−3 or less and serving as an active layer of the semiconductor device with an ion implantation method and thereby forming a drift layer.

摘要翻译： 在通过绝缘膜形成在支撑基板上的SOI型高耐受电压半导体器件的制造方法中，通过将杂质引入p型或者p型的整个表面来制造具有小耐受电压的小分散的小型半导体器件 n型SOI衬底，其杂质浓度为2E14cm-3或更小，并且用离子注入方法用作半导体器件的有源层，从而形成漂移层。

公开(公告)号：US20100327654A1

公开(公告)日：2010-12-30

申请号：US12826409

申请日：2010-06-29

申请人： Katsunori AZUMA ,  Mutsuhiro Mori ,  Michiaki Hiyoshi ,  Seiichi Hayakawa ,  Koji Sasaki ,  Isamu Yoshida

发明人： Katsunori AZUMA ,  Mutsuhiro Mori ,  Michiaki Hiyoshi ,  Seiichi Hayakawa ,  Koji Sasaki ,  Isamu Yoshida

IPC分类号： B60L1/00

CPC分类号： B60L11/04 ,  B60L2200/26 ,  H01L24/28 ,  H01L24/29 ,  H01L24/48 ,  H01L25/072 ,  H01L25/16 ,  H01L2224/48091 ,  H01L2224/4847 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3025 ,  H02M7/003 ,  H03K17/08148 ,  H03K2017/0806 ,  H05K7/1432 ,  Y02T10/70 ,  Y02T10/7077 ,  Y10T307/74 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A power module includes an upper arm circuit unit and a lower arm circuit unit each having a power semiconductor element; an insulating substrate with the units mounted on one surface thereof; a metal base bonded onto the other surface of the substrate opposite to the one surface where the units are mounted; a first connection conductor for supplying a high potential to the upper unit from outside; a second connection conductor for supplying a low potential to the lower unit from outside; an insulating sheet interposed between the conductors; and a resin case disposed on the metal base to support the conductors, the conductors are flat conductors and laminated with the sheet sandwiched therebetween; the sheet extends from one end of the laminated structure to secure the creepage distance between the conductors; and the case is furnished with a recess for containing the laminated structure.

摘要翻译： 功率模块包括上臂电路单元和下臂电路单元，每个具有功率半导体元件; 绝缘基板，其单元安装在其一个表面上; 金属底座粘合到与安装单元的一个表面相对的基板的另一个表面上; 用于从外部向上部单元提供高电位的第一连接导体; 用于从外部向下部单元提供低电位的第二连接导体; 插入在导体之间的绝缘片; 以及设置在金属基座上以支撑导体的树脂壳体，导体是扁平导体，并且夹在其间的片材层压; 片材从层压结构的一端延伸，以确保导体之间的爬电距离; 并且壳体设置有用于容纳层压结构的凹部。

公开(公告)号：US07763974B2

公开(公告)日：2010-07-27

申请号：US10545021

申请日：2004-02-13

申请人： Yoshimasa Takahashi ,  Naoki Sakurai ,  Masashi Yura ,  Masahiro Iwamura ,  Mutsuhiro Mori

发明人： Yoshimasa Takahashi ,  Naoki Sakurai ,  Masashi Yura ,  Masahiro Iwamura ,  Mutsuhiro Mori

IPC分类号： H01L23/34

CPC分类号： H01L25/072 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/162 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H02M1/08 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An integrated circuit for driving a semiconductor device, which is adaptable for demands, such as a higher output (larger current), a higher voltage, and a smaller loss, and has a small size, is produced at a low cost, and has high reliability. A power converter including such an integrated circuit is also provided. Circuit elements constituting a drive section of an upper arm drive circuit 212, a level shift circuit 20 including a current sensing circuit 210, a drive section of a lower arm drive circuit 222, and a drive signal processing circuit 224 are integrated and built in one high withstand voltage IC chip 200. Circuit elements constituting a final output stage buffer section 213 of the upper arm drive circuit 212 are built in a vertical p-channel MOS-FET chip 213p and a vertical n-channel MOS-FET chip 213n. Circuit elements constituting a final output stage buffer section 223 of the lower arm drive circuit 222 are built in a vertical p-channel MOS-FET chip 223p and a vertical n-channel MOS-FET chip 223n. Thus, a driver IC 2 is fabricated.

摘要翻译： 以低成本生产用于驱动半导体器件的集成电路，其具有较高的输出（较大的电流），更高的电压和更小的损耗，并且尺寸更小的需求，并且具有高的 可靠性。 还提供了一种包括这种集成电路的功率转换器。 构成上臂驱动电路212的驱动部的电路元件，包括电流检测电路210的电平移动电路20，下臂驱动电路222的驱动部以及驱动信号处理电路224被一体化并内置于一个 构成上臂驱动电路212的最终输出级缓冲器部分213的电路元件内置在垂直p沟道MOS-FET芯片213p和垂直n沟道MOS-FET芯片213n中。 构成下臂驱动电路222的最终输出级缓冲部分223的电路元件内置在垂直p沟道MOS-FET芯片223p和垂直n沟道MOS-FET芯片223n中。 因此，制造驱动器IC2。

公开(公告)号：US20100149165A1

公开(公告)日：2010-06-17

申请号：US12609258

申请日：2009-10-30

申请人： Takuo NAGASE ,  Mutsuhiro Mori

发明人： Takuo NAGASE ,  Mutsuhiro Mori

IPC分类号： G09G3/28 ,  G09G5/00

CPC分类号： G09G3/296 ,  G09G3/2927 ,  G09G3/293 ,  G09G3/2942 ,  G09G2310/0289 ,  G09G2330/021 ,  G09G2330/028

摘要： A plasma display device of the present invention having a plurality of display cells, comprises a X electrode kept at a reference voltage, a Y electrode, an address electrode, the X electrode and the Y electrode between which sustain discharge occurs, and an address driver comprising a first switch element Q2 for outputting a low level voltage, a second switch element Q1 for outputting a high level voltage, whose withstand voltage of the second switch element is lower than the first switch element, and a diode inserted and connected between the address electrode and the second switch element.

摘要翻译： 具有多个显示单元的本发明的等离子体显示装置包括保持在参考电压的X电极，Y电极，寻址电极，X电极和发生维持放电的Y电极与地址驱动器 包括用于输出低电平电压的第一开关元件Q2，用于输出第二开关元件的耐受电压低于第一开关元件的高电平电压的第二开关元件Q1和插入并连接在地址 电极和第二开关元件。

公开(公告)号：US07570008B2

公开(公告)日：2009-08-04

申请号：US11830051

申请日：2007-07-30

申请人： Masamitsu Inaba ,  Katsunori Azuma ,  Mutsuhiro Mori ,  Kinya Nakatsu

发明人： Masamitsu Inaba ,  Katsunori Azuma ,  Mutsuhiro Mori ,  Kinya Nakatsu

IPC分类号： H02P1/46

CPC分类号： H02M7/003 ,  B60L11/18 ,  B60L15/007 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/49111 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19107 ,  Y02T10/645 ,  Y02T10/7005 ,  H01L2924/00014 ,  H01L2924/00

摘要： The present invention provides a power module, power converter, and vehicular electric machine system capable of reducing inductance of a peripheral section of an output terminal in a power module, and additionally, reducing a surge voltage. A positive emitter conductor 3 connected to an emitter electrode of a positive power semiconductor element Mpu and an output terminal U are electrically interconnected by using a plurality of aluminum wires 7, a negative collector conductor 4 connected to a collector electrode of a negative power semiconductor element Mnu and the output terminal U are electrically interconnected by using a plurality of aluminum wires 9, and the positive emitter conductor 3 connected to the emitter electrode of the positive power semiconductor element Mpu and the negative collector conductor 4 connected to the collector electrode of the negative power semiconductor element Mnu are further electrically interconnected by using a plurality of aluminum wires 8.

摘要翻译： 本发明提供一种功率模块，功率转换器和车载电机系统，其能够降低功率模块中的输出端子的外围部分的电感，并且另外降低浪涌电压。 连接到正功率半导体元件Mpu的发射电极的正的发射极导体3和输出端子U通过使用多个铝线7电连接，负极集电体导体4连接到负功率半导体元件的集电极 Mnu和输出端子U通过使用多个铝线9电连接，并且连接到正功率半导体元件Mpu的发射电极的正发射极导体3和连接到负功率半导体元件Mpu的集电极的负集电极导体4 功率半导体元件Mnu通过使用多根铝线8进一步电互连。