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    Test pad and probe card for wafer acceptance testing and other applications
    5.
    发明申请
    Test pad and probe card for wafer acceptance testing and other applications 审中-公开
    测试垫和探针卡，用于晶圆验收测试等应用

    公开(公告)号：US20060109014A1

    公开(公告)日：2006-05-25

    申请号：US10996242

    申请日：2004-11-23

    申请人： Te-Tsung Chao ,  Chao-Yuan Su ,  Pei-Haw Tsao ,  Chender Huang

    发明人： Te-Tsung Chao ,  Chao-Yuan Su ,  Pei-Haw Tsao ,  Chender Huang

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2891 ,  G01R31/2884

    摘要： A probe card having a member for sending and receiving electrical signals for operational testing of a semiconductor integrated circuit, and a plurality of probe pins extending from the member in a manner which causes free ends of the pins to contact wafer test pads substantially across a maximum dimension of the pads. Also, a test pad for a wafer or a substrate having a pad of electrically conductive material disposed in an area between seal rings of the wafer or substrate, the pad having a shape and/or a rotational orientation within the area between the seal rings that minimizes pad material immediately adjacent the seal rings. Further, a test pad for a wafer or substrate including a passivation layer disposed thereover, the test pad formed of a layer of electrically conductive material and disposed in an opening in the passivation layer, the opening disposed over an uppermost metal layer of the wafer or substrate, the opening and the test pad dimensioned so that the test pad does not contact the passivation layer. Still further, a protection structure for a wafer die core comprising a wafer including a passivation layer and a test pad extending through the passivation layer, and a trench in the passivation layer adjacent to an edge of the test pad.

    摘要翻译： 具有用于发送和接收用于半导体集成电路的操作测试的电信号的构件的探针卡，以及多个探针，所述探针从所述构件延伸，使得所述引脚的自由端基本上跨越最大值接触晶片测试垫 垫的尺寸。 此外，用于晶片或基板的测试焊盘，其具有设置在晶片或基板的密封环之间的区域中的导电材料焊盘，该焊盘在密封环之间的区域内具有形状和/或旋转取向， 最小化紧邻密封环的垫材料。 此外，包括设置在其上的钝化层的晶片或衬底的测试焊盘，所述测试焊盘由导电材料层形成并设置在钝化层的开口中，所述开口设置在晶片的最上层的金属层上，或 衬底，开口和测试焊盘的尺寸设计成使得测试焊盘不接触钝化层。 此外，晶片芯片的保护结构包括包括钝化层的晶片和延伸穿过钝化层的测试焊盘，以及钝化层中邻近测试焊盘边缘的沟槽。

    Process for separating dies on a wafer
    6.
    发明授权
    Process for separating dies on a wafer 有权
    用于在晶片上分离模具的工艺

    公开(公告)号：US06849523B2

    公开(公告)日：2005-02-01

    申请号：US10387285

    申请日：2003-03-12

    申请人： Te-Tsung Chao ,  Shu-Shen Chiu

    发明人： Te-Tsung Chao ,  Shu-Shen Chiu

    IPC分类号： H01L21/301 ,  H01L21/46 ,  H01L21/78

    CPC分类号： H01L21/78 ,  H01L21/6836 ,  H01L2221/68327

    摘要： A process for separating IC dies from a wafer substrate. In one embodiment, complete separation channels are initially cut through the wafer between dies along one axis. Next, partial separation channels are cut into the wafer along an intersecting axis, leaving wafer material connecting adjacent dies. In another embodiment, partial separation channels are cut into the wafer along one axis, after which complete separation channels are cut through the wafer along the intersecting axis. In still another embodiment, partial separation channels are cut along both axes.

    摘要翻译： 用于从晶片衬底分离IC管芯的工艺。 在一个实施例中，完全分离通道最初沿着一个轴线切割穿过管芯之间的晶片。 接下来，沿着交叉轴将部分分离通道切入晶片，留下晶片材料连接相邻的模具。 在另一个实施例中，沿着一个轴将部分分离通道切入晶片，之后沿着相交轴线将整个分离通道切割通过晶片。 在另一个实施例中，沿两个轴切割部分分离通道。